DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-9, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seno et al. (US 2019/0386160).
Regarding claim 1, Seno discloses a back contact solar cell in Figure 3, comprising:
a semiconductor substrate (20) having a light receiving surface (21) and a shady surface (22) opposite to the light receiving surface, the shady surface (22) comprising a first polarity region (60) and a second polarity region (61) that are arranged alternately in a first direction ([21]), the light receiving surface (21) being a textured surface (bumpy texture, [22]), and a surface of the first polarity region (60) and a surface of the second polarity region (70) being polished surfaces ([22], the back surface of the substrate and the surfaces of the polarity regions can be a surface that does not have a bumpy texture, which reads on a polished surface);
a first polarity structure (50 and 70) formed in the first polarity region (60), the first polarity structure comprising a first functional layer (50) and a first electrode structure (70) that are stacked in a direction away from the semiconductor substrate (20), the first functional layer (50) comprising a first passivation layer (50i) and a first doped semiconductor layer (50n) that are stacked in the direction away from the semiconductor substrate (20), and a side surface of the first passivation layer (50i) facing towards the semiconductor substrate being a polished surface (Figure 3 and [32]-[33] and [38], as shown in Figure 3 the first passivation layer is smooth which reads on a polished surface); and
a second polarity structure (51 and 71) formed in the second polarity region (61), the second polarity structure comprising a second functional layer (51) and a second electrode structure (71) that are stacked in the direction away from the semiconductor substrate (20), the second functional layer (51) comprising a second passivation layer (51i) and a second doped semiconductor layer (51p) that are stacked in the direction away from the semiconductor substrate, and a side surface of the second passivation layer (51i) facing towards the semiconductor substrate (20) being a polished surface (Figure 3 and [32], [34] and [38], as shown in Figure 3 the second passivation layer is smooth which reads on a polished surface), wherein a doping type of the first doped semiconductor layer (50n) is opposite to a doping type of the second doped semiconductor layer (51p) (Figure 3 and [31]).
Regarding the limitations recited in claim 1 which are directed to method of making the solar cell (“wherein the surface of the first polarity region of the shady surface is polished to the polished surface from a textured surface, and the surface of the second polarity region of the shady surface is etched into the polished surface after being polished from a textured surface”) it is noted that said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985). As the court stated in Thorpe, 777 F.2d at 697, 227 USPQ at 966 (The patentability of a product does not depend on its method of production. In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969). If the product in a product-by-process claim is the same or obvious as the product of the prior art, the claim is unpatentable even though the prior art product was made by a different process.). See MPEP 2113 and 2114. Seno discloses that the surface of the first polarity region of the shady surface is a polished surface and the surface of the second polarity region of the shady surface is a polished surface ([22], back surface does not have a bumpy texture and reads on a polished surface). Since the solar cell disclosed by Seno has the same polished surface structure of the solar cell recited by claim 1, the claim is unpatentable even though the solar cell of Seno was made by a different process. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983).
Regarding claim 2, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that the second functional layer (51) at least partially extends to the first polarity region (60) (Figure 3 and [31], see overlapping section 64);
a first orthographic projection of the first functional layer (50) on the semiconductor substrate at least partially overlaps with a second orthographic projection of the second functional layer (51) on the semiconductor substrate (Figure 3 and [31], see overlapping section 64); and
the first functional layer (50) is in direct contact with the second functional layer (51) (Figure 3, the functional layers have portions in direct contact); or an insulation layer (52) is arranged between the first functional layer (50) and the second functional layer (51), the insulation layer (52) comprising at least one of phosphorosilicate glass or borosilicate glass, silicon oxide, silicon nitride, or silicon oxynitride (Figure 3 and [31], the overlapping portions of the functional layers are separated by insulating layer 52).
Regarding claim 3, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that a first opening (recess) is formed at the shady surface of the semiconductor substrate (20) and is configured to form the second polarity region (61) (Figures 3 and 8, [52] and [64]).
Regarding claim 4, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that that a second opening is formed at a side of the first doped semiconductor layer (50n) away from the first passivation layer (50i) (Figure 3, See opening for layers 70a and 70b).
Regarding claim 5, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses a third opening (is defined between the first electrode structure (70) and the second electrode structure (71) adjacent to the first electrode structure (See opening in region 64 in Figure 3), a third orthographic projection of the third opening on the semiconductor substrate being located in an overlapping region of the first orthographic projection and the second orthographic projection (region 64 is the overlapping region, Figure 3).
Regarding claim 6, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that the third opening is defined to at least space a first conductive layer (70) of the first electrode structure apart from a second conductive layer (71) of the second electrode structure, and to at most expose the first functional layer (Figure 3, third opening in region 64 spaces apart the first and second conductive layers).
Regarding claim 8, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that the semiconductor substrate (20) further comprises a doped substrate layer (42) located in the first polarity region (60) ([42]) and formed on a side of the first polarity region close to the first passivation layer (50i) (Figure 3), a doping type of the doped substrate layer (42) being the same as the doping type of the first doped semiconductor layer (50n) ([30] and [42], both are first conductivity type), and the doped substrate layer (42) having a thickness ranging from 5 nm to 200 nm ([44], thickness can be 200nm).
Regarding claim 9, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that a distance between the surface of the first polarity region (60) and the light receiving surface (21) is greater than a distance between the surface of the second polarity region (61) and the light receiving surface (21) (Figure 3 and [52], second polarity region is recessed into the substrate which results in a surface of the first polarity region being farther from the substrate than a surface of the second polarity region).
Regarding claim 11, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses a third functional layer (30) and an anti-reflection layer (31) formed on the light-receiving surface (21) of the semiconductor substrate (20) ([25] and [30]), the third functional layer (30) and the anti-reflection layer (31) being stacked in the direction away from the semiconductor substrate (20) (Figure 3), the third functional layer (30) comprising at least one of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped thin film silicon, silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide ([25], 30i is intrinsic amorphous silicon), and the anti- reflection layer (31) comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and transparent conductive oxide ([30]).
Regarding claim 20, Seno discloses a battery assembly in Figure 3 comprising
a back contact solar cell (Figure 3 and [20]) comprising:
a semiconductor substrate (20) having a light receiving surface (21) and a shady surface (22) opposite to the light receiving surface, the shady surface (22) comprising a first polarity region (60) and a second polarity region (61) that are arranged alternately in a first direction ([21]), the light receiving surface (21) being a textured surface (bumpy texture, [22]), and a surface of the first polarity region (60) and a surface of the second polarity region (70) being polished surfaces ([22], the back surface of the substrate and the surfaces of the polarity regions can be a surface that does not have a bumpy texture, which reads on a polished surface);
a first polarity structure (50 and 70) formed in the first polarity region (60), the first polarity structure comprising a first functional layer (50) and a first electrode structure (70) that are stacked in a direction away from the semiconductor substrate (20), the first functional layer (50) comprising a first passivation layer (50i) and a first doped semiconductor layer (50n) that are stacked in the direction away from the semiconductor substrate (20), and a side surface of the first passivation layer (50i) facing towards the semiconductor substrate being a polished surface (Figure 3 and [32]-[33] and [38], as shown in Figure 3 the first passivation layer is smooth which reads on a polished surface); and
a second polarity structure (51 and 71) formed in the second polarity region (61), the second polarity structure comprising a second functional layer (51) and a second electrode structure (71) that are stacked in the direction away from the semiconductor substrate (20), the second functional layer (51) comprising a second passivation layer (51i) and a second doped semiconductor layer (51p) that are stacked in the direction away from the semiconductor substrate, and a side surface of the second passivation layer (51i) facing towards the semiconductor substrate (20) being a polished surface (Figure 3 and [32], [34] and [38], as shown in Figure 3 the second passivation layer is smooth which reads on a polished surface), wherein a doping type of the first doped semiconductor layer (50n) is opposite to a doping type of the second doped semiconductor layer (51p) (Figure 3 and [31]).
Regarding the limitations recited in claim 20 which are directed to method of making the solar cell (“wherein the surface of the first polarity region of the shady surface is polished to the polished surface from a textured surface, and the surface of the second polarity region of the shady surface is etched into the polished surface after being polished from a textured surface”) it is noted that said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985). As the court stated in Thorpe, 777 F.2d at 697, 227 USPQ at 966 (The patentability of a product does not depend on its method of production. In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969). If the product in a product-by-process claim is the same or obvious as the product of the prior art, the claim is unpatentable even though the prior art product was made by a different process.). See MPEP 2113 and 2114. Seno discloses that the surface of the first polarity region of the shady surface is a polished surface and the surface of the second polarity region of the shady surface is a polished surface ([22], back surface does not have a bumpy texture and reads on a polished surface). Since the solar cell disclosed by Seno has the same polished surface structure of the solar cell recited by claim 20, the claim is unpatentable even though the solar cell of Seno was made by a different process. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Seno et al. (US 2019/0386160), as applied to claim 1 above.
Regarding claim 7, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that the first electrode structure (70) comprises a first conductive layer (70a) and a first electrode (70b), the first conductive layer (70a) being located at a side of the first doped semiconductor layer (50n) away from the first passivation layer(50i) (Figure 3 and [39]), and the first electrode (70b) being located at a side of the first conductive layer (70a) away from the first doped semiconductor layer (50n) (Figure 3 and [39]); and the second electrode structure (71) comprises a second conductive layer (71a) and a second electrode (71b), the second conductive layer (71a) being located at a side of the second doped semiconductor layer (51p) away from the second passivation layer (51i) (Figure 3 and [39]), and the first electrode (70b) being located at a side of the second conductive layer (71a) away from the second doped semiconductor layer (51p) (Figure 3 and [39]);
each of a material of the first conductive layer (70a) and the second conductive layer (71a) comprises at least one of zinc oxide, indium oxide, and tin oxide, each of a material of the first conductive layer and the second conductive layer being doped with at least one of gallium element, tin element, titanium element, zirconium element, molybdenum element, cerium element, fluorine element, tungsten element, and aluminum element ([39]).
Seno additionally discloses that a suitable thickness for light transmissive conductive metallic oxide films is 50nm-200nm ([30]). Seno does not disclose that each of the first conductive layer and the second conductive layer have a thickness ranging from 10 nm to 150 nm; however, in the case where the claimed ranges “overlap or lie
inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 10, Seno discloses all of the claim limitations as set forth above. Seno additionally discloses that the first passivation layer (50i) comprises a tunnel oxide ([37]) and has a thickness ranging from 0.5 nm to 2.5 nm (has thickness range of 0.5-20nm, see discussion of overlapping ranges below);
the first doped semiconductor layer (50n) comprises doped polysilicon ([37]) and has a thickness ranging from 10 nm to 250 nm (has thickness range of 2nm-50nm, [33], see discussion of overlapping ranges below);
the second passivation layer (51i) comprises intrinsic amorphous silicon ([34]) and has a thickness ranging from 1 nm to 15 nm (has thickness range of 2nm-50nm, [34], see discussion of overlapping ranges below); and
the second doped semiconductor layer (51p) comprises doped amorphous silicon ([34]) and/or microcrystalline silicon and has a thickness ranging from 1 nm to 60 nm (has thickness range of 2nm-50nm, [34], see discussion of overlapping ranges below).
Seno does not disclose the specifically claimed thickness ranges, but Seno discloses thickness ranges that overlap with the claimed thickness ranges. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Response to Arguments
Applicant's arguments filed 3/23/2026 have been fully considered but they are not persuasive.
Applicant argues that Seno does not disclose “wherein the surface of the first polarity region of the shady surface is polished to the polished surface from a textured surface, and the surface of the second polarity region of the shady surface is etched into the polished surface after being polished from a textured surface” as claimed.
Examiner respectfully disagrees. The limitations “wherein the surface of the first polarity region of the shady surface is polished to the polished surface from a textured surface, and the surface of the second polarity region of the shady surface is etched into the polished surface after being polished from a textured surface” are directed to the method of making the solar cell. Said limitations are not given patentable weight in the product claims. Even though a product-by-process is defined by the process steps by which the product is made, determination of patentability is based on the product itself and does not depend on its method of production. In re Thorpe, 777 F.2d 695, 227 USPQ 964 (Fed. Cir. 1985). As the court stated in Thorpe, 777 F.2d at 697, 227 USPQ at 966 (The patentability of a product does not depend on its method of production. In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969). If the product in a product-by-process claim is the same or obvious as the product of the prior art, the claim is unpatentable even though the prior art product was made by a different process.). See MPEP 2113 and 2114. Seno discloses that the surface of the first polarity region of the shady surface is a polished surface and the surface of the second polarity region of the shady surface is a polished surface ([22], back surface does not have a bumpy texture and reads on a polished surface). Since the solar cell disclosed by Seno has the same polished surface structure of the solar cell recited by claims 1 and 20, the claims are unpatentable even though the solar cell of Seno was made by a different process. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983).
Further, as discussed in MPEP 2113: Once a product appearing to be substantially identical is found and a 35 USC 102/103 rejection made, the burden shifts to the applicant to shown an unobvious difference. "The Patent Office bears a lesser burden of proof in making out a case of prima facie obviousness for product-by-process claims because of their peculiar nature" than when a product is claimed in the conventional fashion. In re Fessmann, 489 F.2d 742, 744, 180 USPQ 324, 326 (CCPA 1974). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983).
The applicant has not provided any evidence that the structure produced by the claimed process is different than the structure of the device of Seno. Therefore, applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDSEY A BUCK whose telephone number is (571)270-1234. The examiner can normally be reached Monday-Friday 9am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Martin can be reached at (571)270-7871. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LINDSEY A BUCK/Primary Examiner, Art Unit 1728
Prosecution Insights