DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 05/24/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 05/24/2024, 09/12/2024, 09/13/2024, 05/30/2025 & 07/25/2025. The information disclosed therein was considered.
Claim Objections
Claims 1-19 are objected to because of the following informalities:
Regarding claims 1 & 19, to be consistent and clear throughout the claim it is suggested to change each instance “a property-variable element,”, to “a one-time programmable (OTP)”, respectively. This allows to define the particular electrical property e.g., OTP. Please see Figure 1 of the current application. Furthermore, the limitations cite “a write control switch, a voltage generation circuit, a noise detection circuit, and a noise discharge switch”, it is suggested to show how these elements are connected to one another. As the claims define an electrical circuit, the claims need to clearly describe how these elements are connected to one another in order to operate and understand how the circuit works.
Regarding claim 7, the limitations cite” further comprising a resistance element connected to the property-variable element in parallel”, suggested to change it to “further comprising a resistance element connected to the OTP in parallel”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 15 & 17-18 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Uchikoba et al (US20030098736).
Regarding claim 1, Uchikoba discloses a semiconductor device comprising(FIG 1; 10): a property-variable element, an electrical property of which changes with application of a voltage equal to or higher than a predetermined voltage to the property-variable element(FIG 1; [0084] discloses 70 wherein VBB is set lowered from voltage higher than detection voltage until it reach the detection voltage) ; a write control switch that switches between a conductive state and a non-conductive state based on a first write control signal for controlling a write to the property-variable element(FIG 1; [0071 discloses 40 switch that turns on when VDD flow to VBB that causes VBB voltage to rise e.g., conductive and off when VBB voltage is not raised e.g., non-conductive). ; a voltage generation circuit that outputs a write voltage from an output terminal of the voltage generation circuit based on a power source and a second write control signal for controlling a write to the property-variable element(FIG 1; voltage generating circuit 50, 30, 20 outputting VBB based on 60 and VCOMPL), the electrical property of the property-variable element being changed due to the application of the voltage equal to or higher than the predetermined voltage to the property-variable element when the write voltage is output from the output terminal of the voltage generation circuit and the write control switch is in the conductive state(40 is turned on and VBB is rising); wiring for use to apply the voltage equal to or higher than the predetermined voltage to the property-variable element FIG 1; [0084] discloses 70 wherein VBB is set lowered from voltage higher than detection voltage until it reach the detection voltage); a noise detection circuit that detects noise at the power source(FIG 1 & 4; 53 & 54 detecting noise at 60); and a noise discharge switch that enables noise current to be discharged from the wiring in an event where the noise detection circuit detects noise at the power source (55 based VCOMPH or VCOMPL at 60, makes up 53 or 54 e.g., switching).
Regarding claim 2, Uchikoba discloses wherein the property-variable element and the write control switch are disposed in series between a first terminal and a second terminal(40 and 70 in series between first terminal at Vdd and second terminal at VBBOUT), the output terminal of the voltage generation circuit and the first terminal are connected to each other via the wiring(Vbb and first terminal connected to wiring), and a potential at the second terminal is a potential that allows that the voltage equal to or higher than the predetermined voltage is applied to the property-variable element when the write voltage is output from the output terminal of the voltage generation circuit and the write control switch is in the conductive state (VBBOUT at second terminal, that is connected to 70 and VBB).
Regarding claim 3, Uchikoba discloses wherein the second terminal is grounded (VBBOUT connected to the second terminal is grounded VSS).
Regarding claim 4, Uchikoba discloses wherein the noise discharge switch is disposed to enable noise current to be discharged through an intermediate node located between the output terminal of the voltage generation circuit and the first terminal on the wiring in an event where the noise detection circuit detects noise at the power source(FIG 1; the wire coming from 20 between VBB and at VDD), and the semiconductor device further comprises a delay element that is disposed between the output terminal of the voltage generation circuit and the intermediate node and that delays noise (FIG 1 & 4; [0091] 55 outputting AMPOUT known as delay time of an amplifier e.g., 55 makes up 53 & 54 and is between the output of 50 and node coming from 20 that is connected to VBB).
Regarding claim 5, Uchikoba discloses wherein the delay element is a resistance element (FIG 1 & 4; R1-R5 making up 53 and 54 that makes up 55).
Regarding claim 6, Uchikoba discloses wherein the noise discharge switch grounds the wiring in an event where the noise detection circuit detects noise at the power source (FIG 4; 55 grounds).
Regarding claim 15, Uchikoba discloses wherein the voltage generation circuit is formed of a p-type high-withstand-voltage transistor (FIG 1 & 4; 50 comprising 53 & 54, and 55 makes up 53 and 54, wherein 55 includes e.g., Q3 PMOS).
Regarding claim 17, Uchikoba disclose wherein a plurality of pairs of the property-variable element and the write control switch are provided for a single set of the voltage generation circuit, the noise detection circuit, and the noise discharge switch (FIG 1; 280 comprising memory cell comprising memory array e.g., memory cells arrange in the array, 50, 30 and 20, wherein 50 comprising 53 54 and 55).
Regarding claim 18, Uchikoba disclose wherein a plurality of pairs of the voltage generation circuit and the noise discharge switch are provided for the single noise detection circuit, and a plurality of pairs of the property-variable element and the write control switch are provided for each of the pairs of the voltage generation circuit and the noise discharge switch (FIG 1; 50, 30 and 20; 50 comprising 3 54 and 55, wherein 55 based VCOMPH or VCOMPL at 60, makes up 53 or 54 e.g., switching).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchikoba et al
Regarding claim 7, Uchikoba discloses further comprising a resistance element (FIG 1; 70 a resistance element and connected to the memory element 80 in series). Even though, Uchikoba does not disclose the resistance element connected to the property-variable element in parallel, the particular placement of the resistance element connected to the property-variable element in parallel was held to be an obvious matter of design choice. Please see MPEP 2144.04.
Therefore, it will obvious to modify Uchikoba to have the resistance element connected to the memory element in parallel.
Regarding claim 8, Uchikoba discloses wherein the resistance element is a diffusion resistance (FIG 1; 70 a diffusion resistance).
Claim(s) 9-12 & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchikoba et al in view of Worley et al (US20100128511).
Regarding claim 9, Uchikoba discloses further comprising that reads the electrical property of the property-variable element (FIG 1; [0082] discloses VBB is stabled 70, data can be read and written e.g., VBBOUT into 80 and 90).
However, Uchikoba does not discloses a read circuit.
In the same field of endeavor, Worley discloses a read circuit (FIG 6; [0025] discloses a read circuit).
Uchikoba and Worley are analogous art because they are all directed to memory device with a resistor, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Uchikoba to include Worley because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Worley in the teachings of Uchikoba for the benefits increasing memory cell density and having a better read out operation without a current leakage. [0007 Worley].
Regarding claim 10, the combination Uchikoba in view of Worley discloses wherein the read circuit includes a current source that generates current and a comparator, and the comparator compares, with a reference voltage, a voltage on the wiring generated in an event where the current is supplied to the property-variable element (FIG 6; [0025] discloses read circuit comprising read current source 609A-B generating current and a comparator 614 comparing reference sense e.g., voltage and a volage e.g., cell sense when current Iread is applied to 605).
Regarding claim 11, the combination Uchikoba in view of Worley discloses wherein the voltage generation circuit and the read circuit are electrically connected to the wiring exclusively (FIG 6; VDD and Iread are electrically connected to wire).
Regarding claim 12, the combination Uchikoba in view of Worley wherein the property-variable element is an antifuse element (FIG 6; [0014] discloses anti-fuse cell), a resistance value of which is changed due to the application of the voltage equal to or higher than the predetermined voltage (FIG 6; [0014 & 0018] discloses anti-fuse cell, wherein anti-fuse changes resistance value when voltage is applied e.g., higher than the Vt).
Regarding claim 16, the combination Uchikoba in view of Worley discloses wherein the power source is supplied from an external connection terminal (FIG 6; Vdd supplied from external terminal pad), and the noise detection circuit is disposed closer to the external connection terminal than any of the voltage generation circuit and the property-variable element is (611 close to terminal of Vdd than 601A in 605).Furthermore, the particular placement of the noise detection circuit in the circuit was held to be an obvious matter of design choice. Please see MPEP 2144.04.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uchikoba et al in view of Taniguchi et al (US20220293199).
Regarding claim 19, Uchikoba discloses comprising (FIG 1; 10): a property-variable element, an electrical property of which changes with application of a voltage equal to or higher than a predetermined voltage to the property-variable element(FIG 1; [0084] discloses 70 wherein VBB is set lowered from voltage higher than detection voltage until it reach the detection voltage) ; a write control switch that switches between a conductive state and a non-conductive state based on a first write control signal for controlling a write to the property-variable element(FIG 1; [0071 discloses 40 switch that turns on when VDD flow to VBB that causes VBB voltage to rise e.g., conductive and off when VBB voltage is not raised e.g., non-conductive). ; a voltage generation circuit that outputs a write voltage from an output terminal of the voltage generation circuit based on a power source and a second write control signal for controlling a write to the property-variable element(FIG 1; voltage generating circuit 50, 30, 20 outputting VBB based on 60 and VCOMPL), the electrical property of the property-variable element being changed due to the application of the voltage equal to or higher than the predetermined voltage to the property-variable element when the write voltage is output from the output terminal of the voltage generation circuit and the write control switch is in the conductive state(40 is turned on and VBB is rising); wiring for use to apply the voltage equal to or higher than the predetermined voltage to the property-variable element FIG 1; [0084] discloses 70 wherein VBB is set lowered from voltage higher than detection voltage until it reach the detection voltage); a noise detection circuit that detects noise at the power source(FIG 1 & 4; 53 & 54 detecting noise at 60); and a noise discharge switch that enables noise current to be discharged from the wiring in an event where the noise detection circuit detects noise at the power source (55 based VCOMPH or VCOMPL at 60, makes up 53 or 54 e.g., switching).
However, Uchikoba does not disclose an inkjet printing element substrate.
In the same field of endeavor, Taniguchi discloses an inkjet printing element substrate (FIG 1-2; [0029 & 0032] discloses 1000 including printhead unit 20, that stores a printing material (ink) to be supplied to the printhead 10).
Uchikoba and Taniguchi are analogous art because they are all directed to a memory device comprising memory element for writing and reading data, and one of ordinary skill in the art would have had a reasonable expectation of success by modify to include because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Taniguchi in the teachings of Uchikoba for the benefits preventing an operation error of the memory device and providing a reliably write data to the memory device [0005-0006 Taniguchi].
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al (US20110058439 FIG 4-5 & 8A; discloses memory comprising a memory array 140, having power supply 180 providing both to 120 and 140, wherein 140 receive a voltage greater than power supply from charge pump).
Gogl et al (US2008002481 FIG 4b & 10a; discloses memory array and sources of noise, such as noise from power supplies, output buffers, or internal switching noise of the memory device, wherein memory cell remains within defined switching state even if voltage /inverse voltage has been removed).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827