DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wrathall (US 2004/0021450 A1).
Regarding Claim 1, Wrathall discloses a current buffer comprising:
1[a]: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to an input current; (Wrathall discloses a current replication circuit configured to generate intermediate currents at first and second nodes according to an input current; see Fig. 12A, NMOS differential pair transistors MN15a, MN16a driven by input/converted nodes 1204, 1206; paragraph [0087]);
1[b]: a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate an output current according to a current flowing through the first node; (Wrathall discloses a first impedance biasing circuit coupled to the first node providing a first input impedance and generating an output current; see Fig. 12B, PMOS transistor MP23a/MP26a mirror/converter at node 1208; paragraph [0088]);
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Fig. 12A of Wrathall annotated by the examiner for ease of reference.
1[c]: a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and (Wrathall discloses a second impedance biasing circuit coupled to the second node providing a second input impedance; see Fig. 12A, bias network including transistors MP20a, MP22a, R70, C55 at node 1204/differential stage; paragraphs [0085]-[0087]);
1[d]: a first feedforward capacitor coupled between the first node and the second node; (Wrathall discloses a first feedforward capacitor coupled between the nodes; see Fig. 12A, capacitor C55 coupled between input/intermediate differential nodes; paragraph [0087]);
1[e]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (Wrathall discloses impedance relationships yielding a zero and a pole in the gain response; see Fig. 12A-12B; paragraphs [0046]-[0050], [0086]-[0088]);
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Fig. 12B of Wrathall annotated by the examiner for ease of reference.
1[f]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (Wrathall discloses a zero frequency lower than the pole frequency; see Fig. 4, Fig. 18; paragraphs [0048]-[0050], [0103]);
1[g]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (Wrathall discloses the zero and/or pole frequencies correlated with the capacitance value and impedance; see Fig. 12A-12B; paragraphs [0046]-[0050], [0087]).
Regarding Claim 14, Wrathall further teaches an amplifier circuit comprising:
14[a]: Alternative 1: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the pre-amplification signal, wherein the output stage circuit includes a current buffer, wherein an input current of the current buffer is generated according to the pre-amplification signal, and the post-amplification signal corresponds to an output current of the current buffer;
OR Alternative 2: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; an intermediate amplification circuit configured to operably amplify the pre-amplification signal to generate an intermediate amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the intermediate amplification signal; wherein the intermediate amplification circuit includes the current buffer, wherein the input current of the current buffer is generated according to the pre-amplification signal, and the intermediate amplification signal is generated according to the output current of the current buffer; (Wrathall discloses Alternative 2: a pre-amplification circuit (Fig. 8, first gain stage 820), an intermediate amplification circuit including a current buffer (Fig. 8, zero generation circuit 810 / Fig. 12 stage), and an output stage circuit (Fig. 8, second stage 824); paragraphs [0064]-[0068], [0085]-[0088]);
14[b] (Current Buffer limitations): wherein the current buffer includes: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to the input current; a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate the output current according to a current flowing through the first node; a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and a first feedforward capacitor coupled between the first node and the second node; (Wrathall discloses each current buffer limitation as detailed in claim 1[a]-1[d] above; see Fig. 12A-12B; paragraphs [0085]-[0088]);
14[c]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (Wrathall discloses this limitation as detailed in claim 1[e] above; see Fig. 12A-12B; paragraphs [0046]-[0050]);
14[d]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (Wrathall discloses this limitation as detailed in claim 1[f] above; see Fig. 4, Fig. 18; paragraphs [0048]-[0050]);
14[e]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (Wrathall discloses this limitation as detailed in claim 1[g] above; see Fig. 12A-12B; paragraphs [0046]-[0050], [0087]).
Regarding Claim 15 Wrathall further teaches an amplifier circuit comprising:
15[a]: Alternative 1: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the pre-amplification signal, wherein the output stage circuit includes a current buffer, wherein an input current of the current buffer is generated according to the pre-amplification signal, and the post-amplification signal corresponds to an output current of the current buffer;
OR Alternative 2: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; an intermediate amplification circuit configured to operably amplify the pre-amplification signal to generate an intermediate amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the intermediate amplification signal; wherein the intermediate amplification circuit includes the current buffer, wherein the input current of the current buffer is generated according to the pre-amplification signal, and the intermediate amplification signal is generated according to the output current of the current buffer; (Wrathall discloses Alternative 2 as detailed in claim 14[a] above; see Fig. 8; paragraphs [0064]-[0068]);
15[b] (Feedback circuit limitation): wherein the amplifier circuit further includes a feedback circuit configured to operably generate a feedback signal according to the post-amplification signal, wherein the differential input signal corresponds to a difference between the feedback signal and a reference signal, wherein the amplifier circuit regulates the post-amplification signal to a target level according to the feedback signal, the target level being correlated with the reference signal; (Wrathall discloses a feedback circuit generating a feedback signal to regulate the output signal relative to a reference signal; see Fig. 8, feedback terminal 804, divider resistors R1/R2, node 806 providing VFB compared with Vref; paragraphs [0042], [0065]);
15[c] (Current Buffer limitations): wherein the current buffer includes: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to the input current; a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate the output current according to a current flowing through the first node; a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and a first feedforward capacitor coupled between the first node and the second node; (Wrathall discloses each current buffer limitation as detailed in claim 1[a]-1[d] above; see Fig. 12A-12B; paragraphs [0085]-[0088]);
15[d]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (Wrathall discloses this limitation as detailed in claim 1[e] above; see Fig. 12A-12B; paragraphs [0046]-[0050]);
15[e]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (Wrathall discloses this limitation as detailed in claim 1[f] above; see Fig. 4, Fig. 18; paragraphs [0048]-[0050]);
15[f]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (Wrathall discloses this limitation as detailed in claim 1[g] above; see Fig. 12A-12B; paragraphs [0046]-[0050], [0087]).
Claims 1, 14, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DeCremoux (US 2006/0012451 A1).
Regarding Claim 1, DeCremoux discloses a current buffer comprising:
1[a]: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to an input current; (DeCremoux teaches a current replication/mirror circuit 27 comprising transistors 33 and 34 that generates a first intermediate current I27 at a first node [drain of 31/33] and a second intermediate current IS at a second node [drain of 34] according to an input current VIN / current through terminal 21; FIG. 2, FIG. 3, FIG. 6 [item 150], [0028], [0036]–[0038]).
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Figs. 2(left) and 3 (right) of DeCremoux annotated by the examiner for ease of reference.
1[b]: a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate an output current according to a current flowing through the first node; (DeCremoux teaches a first impedance biasing/amplifying element 26/31 coupled to the first node [drain of 31/33] configured to provide a first input impedance at the first node and generate an output current IOUT at terminal 22 according to a current flowing through the first node; FIG. 2, FIG. 3, FIG. 6, [0028], [0031]–[0032], [0036]).
1[c]: a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and (DeCremoux teaches a second impedance biasing circuit/loop 28/29 comprising current mirror transistors 35, 36 coupled to the second node [drain of 34] and configured to provide a second input impedance at the second node; FIG. 2, FIG. 3, FIG. 6, [0028], [0030], [0039]).
1[d]: a first feedforward capacitor coupled between the first node and the second node; (DeCremoux teaches a feedback/feedforward capacitor 23 coupled between the input terminal 21/first node and high-impedance node N/second node; FIG. 2, FIG. 3, FIG. 6, [0027]–[0028]).
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1[e]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (DeCremoux teaches that node N has a high impedance relative to other internal nodes [e.g., node N is at least 10 MΩ], inherently providing the low vs. high impedance relationship at the nodes that establishes the zero and pole response of the AC current transfer characteristic; FIG. 2, FIG. 3, [0012], [0027]–[0028], [0036]).
1[f]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (DeCremoux inherently teaches that the first zero frequency is lower than the first pole frequency to provide dominant-pole/zero phase compensation across operating frequencies; FIG. 2, FIG. 6, [0005]–[0008], [0027]–[0029]).
1[g]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (DeCremoux teaches that the effective capacitive feedback response, zero/pole frequencies, and loop stability are directly correlated with the capacitance value of capacitor 23 and the high impedance of node N; FIG. 2, FIG. 3, [0008]–[0012], [0027]–[0029]).
Regarding Claim 14, DeCremoux teaches an amplifier circuit comprising:
14[a]: Alternative 2: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; an intermediate amplification circuit configured to operably amplify the pre-amplification signal to generate an intermediate amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the intermediate amplification signal; wherein the intermediate amplification circuit includes the current buffer, wherein the input current of the current buffer is generated according to the pre-amplification signal, and the intermediate amplification signal is generated according to the output current of the current buffer; (DeCremoux teaches a multi-stage voltage regulator/amplifier circuit 100 [FIG. 6] comprising a pre-amplification differential input stage 110 that amplifies a differential input signal to generate a pre-amplification signal at output node 119/61 [FIG. 6, [0067]]; an intermediate stage/current buffer circuit 150/20 coupled to inter-stage node 119/61 that amplifies the pre-amplification signal to generate an intermediate amplification signal at terminal 22 [FIG. 6, [0068], [0070]]; and an output stage driver circuit 130 that generates a post-amplification output signal VOUT at terminal 132 according to the intermediate signal [FIG. 6, [0068]–[0070]]).
14[b] (Current Buffer limitations): wherein the current buffer includes: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to the input current; a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate the output current according to a current flowing through the first node; a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and a first feedforward capacitor coupled between the first node and the second node; (DeCremoux teaches these limitations as mapped in claim elements 1[a]–1[d] above; FIG. 2, FIG. 3, FIG. 6 [item 150], [0028], [0030]–[0039]).
14[c]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (DeCremoux teaches this limitation as mapped in claim element 1[e] above; FIG. 2, FIG. 3, [0012], [0027]–[0028], [0036]).
14[d]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (DeCremoux teaches this limitation as mapped in claim element 1[f] above; FIG. 2, FIG. 6, [0005]–[0008], [0027]–[0029]).
14[e]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (DeCremoux teaches this limitation as mapped in claim element 1[g] above; FIG. 2, FIG. 3, [0008]–[0012], [0027]–[0029]).
Regarding Claim 15, DeCremoux teaches an amplifier circuit comprising:
15[a]: Alternative 2: a pre-amplification circuit configured to operably amplify a differential input signal to generate a pre-amplification signal; an intermediate amplification circuit configured to operably amplify the pre-amplification signal to generate an intermediate amplification signal; and an output stage circuit configured to operably generate a post-amplification signal according to the intermediate amplification signal; wherein the intermediate amplification circuit includes the current buffer, wherein the input current of the current buffer is generated according to the pre-amplification signal, and the intermediate amplification signal is generated according to the output current of the current buffer; (DeCremoux teaches this limitation as mapped in claim element 14[a] above; FIG. 6, [0067]–[0070]).
15[b] (Feedback circuit limitation): wherein the amplifier circuit further includes a feedback circuit configured to operably generate a feedback signal according to the post-amplification signal, wherein the differential input signal corresponds to a difference between the feedback signal and a reference signal, wherein the amplifier circuit regulates the post-amplification signal to a target level according to the feedback signal, the target level being correlated with the reference signal; (DeCremoux teaches a resistive voltage divider feedback circuit 140 coupled between output terminal 132 and feedback input terminal 122 of differential input stage 120/110 to generate a feedback signal representing VOUT; differential input stage 120 receives a reference signal at input terminal 121 and amplifies the difference between the feedback signal and the reference signal to regulate VOUT to a target voltage level; FIG. 1A, FIG. 6, [0003], [0067], [0069]).
15[c] (Current Buffer limitations): wherein the current buffer includes: a current replication circuit configured to operably generate a first intermediate current at a first node and a second intermediate current at a second node according to the input current; a first impedance biasing circuit coupled to the first node and configured to operably provide a first input impedance at the first node and generate the output current according to a current flowing through the first node; a second impedance biasing circuit coupled to the second node and configured to operably provide a second input impedance at the second node; and a first feedforward capacitor coupled between the first node and the second node; (DeCremoux teaches these limitations as mapped in claim elements 1[a]–1[d] above; FIG. 2, FIG. 3, FIG. 6 [item 150], [0028], [0030]–[0039]).
15[d]: wherein the first input impedance is lower than the second input impedance, such that a current gain between the output current and the input current has a first zero and a first pole, (DeCremoux teaches this limitation as mapped in claim element 1[e] above; FIG. 2, FIG. 3, [0012], [0027]–[0028], [0036]).
15[e]: wherein a first zero frequency of the first zero is lower than a first pole frequency of the first pole, (DeCremoux teaches this limitation as mapped in claim element 1[f] above; FIG. 2, FIG. 6, [0005]–[0008], [0027]–[0029]).
15[f]: wherein the first zero frequency and/or the first pole frequency is correlated with a capacitance value of the first feedforward capacitor and an impedance value of the second input impedance. (DeCremoux teaches this limitation as mapped in claim element 1[g] above; FIG. 2, FIG. 3, [0008]–[0012], [0027]–[0029]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7 and 8 are rejected under 35 U.S.C. 103(a) as being obvious over DeCremoux (US 2006/0012451 A1) in view of Bourque (US 2024/0022213 A1).
Regarding Claim 7, DeCremoux teaches all limitations of claim 1, and further discloses current replication circuit 27 comprising transistors 33 and 34 (FIG. 2, FIG. 3, [0028], [0036]–[0038]). DeCremoux, however, is not explicit about the current replication circuit being a current mirror configured to operably mirror the input current to generate the first intermediate current and the second intermediate current.
Bourque in a similar field of endeavor of current amplification circuit teaches current mirrors configured to operably mirror input currents into first and second intermediate currents (e.g., current mirror connections 31/41 in FIG. 4, FIG. 5, FIG. 6).
It would be obvious to a POSITA to implement DeCremoux's replication circuit 27 as a current mirror, as taught by Bourque (FIG. 4, item 31; FIG. 5, item 41) because current mirrors are well-known, simple, and reliable circuit structures that provide accurate linear current copying across supply and temperature variations.
Regarding Claim 8, DeCremoux teaches all limitations of claim 1, and further discloses a current buffer circuit. DeCremoux, however, is not explicit that the current replication circuit is a current buffer circuit which is configured to operably buffer the input current through at least one buffer transistor to generate the first intermediate current and is configured to operably mirror the input current to generate the second intermediate current.
Bourque teaches current buffer architectures wherein an input current is buffered through at least one cascode/buffer transistor (e.g., folded cascode transistor MN\CAS connected to node A, FIG. 1) to generate a first intermediate current, while simultaneously mirroring the input current via mirror transistors (e.g., MN\ISRC, MP1/MP2) to generate a second intermediate current at a secondary node.
It would be obvious to a POSITA to modify DeCremoux's replication circuit 27 to combine a direct buffer transistor path for the first intermediate current with a mirrored branch for the second intermediate current, as taught by Bourque.
A POSITA would be motivated to combine buffered pass-through with current mirroring as taught by Bourque to achieve high input bandwidth, low input impedance at the primary sensing node, and isolation of high-frequency compensation current paths.
Claim 9 and 11 are rejected under 35 U.S.C. 103(a) as being obvious over DeCremoux (US 2006/0012451 A1) in view of Hurrell (US 2025/0044820 A1).
Regarding Claim 9, DeCremoux teaches all limitations of claim 1, and further discloses first impedance biasing circuit 26/31 and second impedance biasing circuit 28/29. DeCremoux, however, is not explicit that at least one of the first impedance biasing circuit and the second impedance biasing circuit is a voltage regulator circuit and the corresponding first node or second node is a regulation node wherein the voltage regulator circuit is configured to operably regulate a voltage at the regulation node to a target voltage according to a bias voltage.
Hurrell, in a similar field of endeavor, teaches buffer and impedance biasing circuits operating as voltage regulation stages (FIG. 3, FIG. 4a, [0032]–[0045]). Hurrell discloses voltage regulator circuits comprising active feedback/cascode regulation networks configured to regulate a node to a target voltage according to a bias reference voltage (FIG. 4a, items MP14, MP15, MN1, MN4, [0040]–[0045]).
It would have been obvious to a POSITA to modify at least one of the impedance biasing circuits (26/31 or 28/29) of DeCremoux to be a voltage regulator circuit that regulates the voltage at the node to a target bias voltage, as taught by Hurrell.
A POSITA would be motivated to replace standard biasing elements with an active voltage regulator circuit as taught by Hurrell to stabilize node operating voltages, reduce transient glitching during current switching, and improve supply voltage noise rejection (PSRR).
Regarding Claim 11, DeCremoux teaches all limitations of claim 1, and DeCremoux, however, is not explicit that the voltage regulator circuit includes an error amplifier and an impedance control transistor wherein the error amplifier is configured to operably amplify a difference between the voltage at the regulation node and the bias voltage to generate an error amplification signal, and the error amplification signal controls the impedance control transistor which regulates the voltage at the regulation node to the target voltage.
Hurrell teaches active voltage regulation loops comprising an error amplifier / transconductance stage (MP14, MN1, MP10, FIG. 4a, [0041]–[0046]) and an impedance control transistor (MP1, FIG. 4a). Hurrell explicitly discloses amplifying the voltage difference between a regulation node and a reference/bias voltage to generate an error amplification signal at the gate of an impedance control transistor (MP1), which in turn regulates the node to the target voltage.
A POSITA would find it obvious to incorporate the error amplifier and impedance control transistor active regulation loop of Hurrell (FIG. 4a) into the impedance biasing node of DeCremoux.
A POSITA would be motivated to incorporate active error amplifier feedback as taught by Hurrell to achieve extremely precise voltage regulation at the node, minimize DC offset errors, and suppress AC power supply ripple by forcing AC disturbing currents to zero.
Claims 10 is rejected under 35 U.S.C. 103(a) as being obvious over DeCremoux (US 2006/0012451 A1) in view of Bourque (US 2024/0022213 A1) and Hurrell (US 2025/0044820 A1).
Regarding Claim 10, DeCremoux teaches all limitations of claim 1, and further discloses transistor biasing stages. DeCremoux, however, is not explicit that the voltage regulator circuit is a common-gate amplifier stage circuit or a diode-connected transistor.
Both Bourque and Hurrell teach voltage regulation/biasing stages implemented using common-gate amplifier transistors (e.g., folded cascode MN\CAS in Bourque FIG. 1; MP14 in Hurrell FIG. 4a) or diode-connected transistors (e.g., MP15 in Hurrell FIG. 4a, [0041]).
It would have been obvious to a POSITA to construct the voltage regulator/biasing circuit of DeCremoux as a common-gate amplifier stage or a diode-connected transistor as taught by Bourque and Hurrell.
A POSITA would use a common-gate stage or diode-connected transistor as taught by Bourque and Hurrell because these structures represent elementary, highly compact circuit configurations providing reliable voltage level shifting and low input impedance.
Claims 21 and 22 are rejected under 35 U.S.C. 103(a) as being unpatentable over DeCremoux in view of Bourque.
Regarding Claim 21, DeCremoux teaches all limitations of claim 15, and further discloses current replication circuit 27 comprising transistors 33 and 34 (FIG. 2, FIG. 3, [0028], [0036]–[0038]). DeCremoux, however, is not explicit about the current replication circuit being a current mirror configured to operably mirror the input current to generate the first intermediate current and the second intermediate current.
Bourque in a similar field of endeavor of current amplification circuit teaches current mirrors configured to operably mirror input currents into first and second intermediate currents (e.g., current mirror connections 31/41 in FIG. 4, FIG. 5, FIG. 6).
It would be obvious to a POSITA to implement DeCremoux's replication circuit 27 as a current mirror, as taught by Bourque (FIG. 4, item 31; FIG. 5, item 41) because current mirrors are well-known, simple, and reliable circuit structures that provide accurate linear current copying across supply and temperature variations.
Regarding Claim 22, DeCremoux teaches all limitations of claim 15, and further discloses a current buffer circuit. DeCremoux, however, is not explicit that the current replication circuit is a current buffer circuit which is configured to operably buffer the input current through at least one buffer transistor to generate the first intermediate current and is configured to operably mirror the input current to generate the second intermediate current.
Bourque teaches current buffer architectures wherein an input current is buffered through at least one cascode/buffer transistor (e.g., folded cascode transistor MN_CAS connected to node A, FIG. 1) to generate a first intermediate current, while simultaneously mirroring the input current via mirror transistors (e.g., MN_ISRC, MP1/MP2) to generate a second intermediate current at a secondary node.
It would be obvious to a POSITA to modify DeCremoux's replication circuit 27 to combine a direct buffer transistor path for the first intermediate current with a mirrored branch for the second intermediate current, as taught by Bourque.
A POSITA would be motivated to combine buffered pass-through with current mirroring as taught by Bourque to achieve high input bandwidth, low input impedance at the primary sensing node, and isolation of high-frequency compensation current paths.
Claims 23 and 25 are rejected under 35 U.S.C. 103(a) as being unpatentable over DeCremoux in view of Hurrell.
Regarding Claim 23, DeCremoux teaches all limitations of claim 15, and further discloses first impedance biasing circuit 26/31 and second impedance biasing circuit 28/29. DeCremoux, however, is not explicit that at least one of the first impedance biasing circuit and the second impedance biasing circuit is a voltage regulator circuit and the corresponding first node or second node is a regulation node wherein the voltage regulator circuit is configured to operably regulate a voltage at the regulation node to a target voltage according to a bias voltage.
Hurrell, in a similar field of endeavor, teaches buffer and impedance biasing circuits operating as voltage regulation stages (FIG. 3, FIG. 4a, [0032]–[0045]). Hurrell discloses voltage regulator circuits comprising active feedback/cascode regulation networks configured to regulate a node to a target voltage according to a bias reference voltage (FIG. 4a, items MP14, MP15, MN1, MN4, [0040]–[0045]).
It would have been obvious to a POSITA to modify at least one of the impedance biasing circuits (26/31 or 28/29) of DeCremoux to be a voltage regulator circuit that regulates the voltage at the node to a target bias voltage, as taught by Hurrell.
A POSITA would be motivated to replace standard biasing elements with an active voltage regulator circuit as taught by Hurrell to stabilize node operating voltages, reduce transient glitching during current switching, and improve supply voltage noise rejection (PSRR).
Regarding Claim 25, DeCremoux teaches all limitations of claim 15 and 23. DeCremoux, however, is not explicit that the voltage regulator circuit includes an error amplifier and an impedance control transistor wherein the error amplifier is configured to operably amplify a difference between the voltage at the regulation node and the bias voltage to generate an error amplification signal, and the error amplification signal controls the impedance control transistor which regulates the voltage at the regulation node to the target voltage.
Hurrell teaches active voltage regulation loops comprising an error amplifier / transconductance stage (MP14, MN1, MP10, FIG. 4a, [0041]–[0046]) and an impedance control transistor (MP1, FIG. 4a). Hurrell explicitly discloses amplifying the voltage difference between a regulation node and a reference/bias voltage to generate an error amplification signal at the gate of an impedance control transistor (MP1), which in turn regulates the node to the target voltage.
A POSITA would find it obvious to incorporate the error amplifier and impedance control transistor active regulation loop of Hurrell (FIG. 4a) into the impedance biasing node of DeCremoux.
A POSITA would be motivated to incorporate active error amplifier feedback as taught by Hurrell to achieve extremely precise voltage regulation at the node, minimize DC offset errors, and suppress AC power supply ripple by forcing AC disturbing currents to zero.
Claim 24 is rejected under 35 U.S.C. 103(a) as being unpatentable over DeCremoux in view of Bourque and Hurrell.
Regarding Claim 24, DeCremoux teaches all limitations of claim 15 and 23, and further discloses transistor biasing stages. DeCremoux, however, is not explicit that the voltage regulator circuit is a common-gate amplifier stage circuit or a diode-connected transistor.
Both Bourque and Hurrell teach voltage regulation/biasing stages implemented using common-gate amplifier transistors (e.g., folded cascode MN_CAS in Bourque FIG. 1; MP14 in Hurrell FIG. 4a) or diode-connected transistors (e.g., MP15 in Hurrell FIG. 4a, [0041]).
It would have been obvious to a POSITA to construct the voltage regulator/biasing circuit of DeCremoux as a common-gate amplifier stage or a diode-connected transistor as taught by Bourque and Hurrell.
A POSITA would use a common-gate stage or diode-connected transistor as taught by Bourque and Hurrell because these structures represent elementary, highly compact circuit configurations providing reliable voltage level shifting and low input impedance.
Allowable Subject Matter
Claims 2-6, 12-13, 16-20 and 26-27 are objected to as being dependent upon a rejected base claim 1 and 15 respectively but would be allowable if rewritten in independent form including all the limitations of base claims 1 and 15 and any intervening claims.
The primary reference, DeCremoux, fails to disclose the complex mathematical pole-zero relationships, capacitance dominance criteria, multi-path frequency transfer functions, and Miller compensation feedback loops recited in these claims. Attempting to combine DeCremoux with Bourque or Hurrell to reach these specific features requires reconstructive hindsight, as neither Bourque nor Hurrell teaches these specific mathematical and structural constraints in the manner claimed. Neither DeCremoux nor Bourque explicitly discloses or suggests the specific high-frequency current gain transfer function driven by a linear superposition ratio of mirrored intermediate currents as recited in claims 2-5.
Claim 6 a multi-path compensation scheme including a third impedance biasing circuit, a third node, a second feedforward capacitor coupled between the first and third nodes and establishing a second pole and second zero whose frequencies are dictated by the second feedforward capacitor and third node impedance.
Combining DeCremoux with Bourque to add a third biasing path and second feedforward capacitor creating a second pole/zero pair requires fundamental modification of DeCremoux's core topology. Bourque’s multi-path arrangements (e.g., rail-to-rail complementary structures in FIG. 2) do not teach or suggest the specific asymmetric impedance relationship (Z1 < Z3) and second pole/zero transfer function recited.
Claims 12-13 recites a capacitive input replication circuit comprising first and second compensation capacitors coupled from an input node to first and second nodes, respectively, which directly generate the input current and intermediate currents at these nodes according to the input voltage. Bourque discloses feedforward compensation capacitors, but does not disclose a input/replication structure where a pair of compensation capacitors directly converts input voltage to generate the primary input current alongside both the first and second intermediate currents directly at internal biasing nodes.
Claims 16–20 and 26–27 recite specific mathematical frequency relationships, compensation node connections, or multi-capacitor feedforward topologies that are not disclosed or rendered obvious by the cited references.
Conclusion
The prior art, US5982226_Rincon_Mora, US6573790_SteenGaard-Madsen, US20040169550_Perrier, US20120182075_Ivanov, US20190258283_Pishdad, US20220038000_Shuvalov, made of record and not relied upon is considered pertinent to applicant's disclosure.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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