DETAILED ACTION
Claims 1-24 are presented for examination.
Claims 6, 8, 14, 17 are canceled.
This office action is in response to request for continued examination of application on 1-APRIL-2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1-APRIL-2026 has been entered.
Response to Arguments
Applicant’s arguments, see page 8, filed 1-APRIL-2026, with respect to the objections to the claims have been fully considered and are persuasive due to amendments. The objections to the claims have been withdrawn.
Applicant’s arguments, see page 8, filed 1-APRIL-2026, with respect to the non-statutory double patenting rejections have been fully considered and are persuasive due to the filing of a Terminal Disclaimer on 1-APRIL-2026 which was approved on 29-APRIL-2026. The non-statutory double patenting rejections have been withdrawn.
Applicant's arguments filed 1-APRIL-2026 have been fully considered but they are not persuasive.
Regarding applicant’s argument that the prior art does not teach the newly amended limitations of the preamble and prologue tag memories being different tag memories having dedicated corresponding circuitry, Examiner respectfully disagrees.
Firstly, contrary to what Applicant argues the result of the amendment is, the broadest reasonable interpretation of “having dedicated corresponding circuitry” does not specify how much or which of the corresponding circuitry must be dedicated. In other words, a single component dedicated to the preamble tag memories and a different single component dedicated to the prologue tag memories is sufficient to meet the limitation. Accordingly, Chofleming teaches that the primary tag memory (preamble tag memory) is one type of memory, and the secondary tag memory (prologue tag memory) is another type of memory, clearly showing that the primary and secondary tag memories have at least one kind of dedicated corresponding circuitry.
Secondly, the broadest reasonable interpretation of “the preamble tag memory and the prologue tag memory are different tag memories” encompasses any kind of component or functionality that distinguishes the preamble tag memory and prologue tag memory in any way. In other words, there is no limitation which describes specifically how these memories differ or what it means for the tag memories to be different. Accordingly, Chofleming teaches the primary tag memory and secondary tag memory having distinct components that perform different functions of storing different types of data, which are used in different stages of the invention of Chofleming, and therefore, the primary tag memory and secondary tag memories are understood to be different tag memories.
Therefore, the amendments to the independent claims do not distinguish the claims from the previously applied prior art references and do not overcome the prior art, and the rejections under 35 U.S.C. 103 are maintained for the independent claims and claims which depend upon them.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 9-13, 15, 16, 18, 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over
CHOFLEMING et al., U.S. Pub. No. 20220283948 (hereinafter “Chofleming”) in view of
Asadi et al., U.S. Pub. No. 20210201974 (hereinafter “Asadi”).
Regarding claim 1: Chofleming teaches A system for performing tag way halting comprising:
a memory subsystem including a preamble tag memory and one or more prologue tag memories for one or more ways (Fig. 5 and [0044], Chofleming teaches a cache subsystem with a primary tag memory and secondary tag memory).
the preamble tag memory and the one or more prologue tag memories are different tag memories having dedicated corresponding circuitry ([0050] and [0068-0069], Chofleming teaches two different primary tag memory and secondary tag memory elements with different purposes, storing different data, and being used in different steps of the process, with an example embodiment showing them being implemented on entirely different memory technologies, which is interpreted to mean that the tag memories are different tag memories with dedicated corresponding circuitry)
the preamble tag memory comprises: a preamble memory array, (Fig. 5 and [0044], Chofleming teaches a primary tag memory 580)
a preamble memory control circuit, (Fig. 5 and [0048], Chofleming teaches a controller 523 that controls the primary tag memory 580)
a preamble memory input/output circuitry, and (Fig. 5 and [0048], Chofleming teaches IO 501)
a preamble hit circuitry (Fig. 5 and [0050], Chofleming teaches a primary tag match component 550)
wherein the preamble tag memory stores a first set of bits from a tag portion of a plurality of addresses stored at the memory subsystem, (Fig. 5 and [0050], Chofleming teaches that primary tags are stored in the primary tag memory 580)
a wherein the one or more prologue tag memories each comprises ([0020], Chofleming teaches secondary tag memory components corresponding to each cache line)
a prologue memory array, (Fig. 5 and [0044], Chofleming teaches a secondary tag memory 580.)
a prologue memory control circuit, (Fig. 5 and [0048], Chofleming teaches a controller 523 that controls the secondary tag memory 585)
a prologue memory input/output circuitry, and (Fig. 5 and [0048], Chofleming teaches IO 501)
a prologue hit circuitry (Fig. 5 and [0050], Chofleming teaches a secondary tag match component 555)
wherein the one or more prologue tag memories store a second set of bits from the tag portion and memory data information of the plurality of addresses, (Fig. 5 and [0050], Chofleming teaches that secondary tags are stored in the secondary tag memory 585. Moreover, in [0027], Chofleming teaches that when secondary tags are found, there is a corresponding data made available for that cache line.)
While Chofleming teaches matching a received primary lookup tag 535 and a received secondary tag to such tags in primary and secondary tag memory, Chofleming does not appear to explicitly disclose a preamble memory wordline driver, wherein the preamble memory hit circuitry performs a comparison of preamble bits of a received address and the stored first set of bits from the tag portion in the preamble tag memory, and a prologue memory wordline driver, wherein the prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored second set of bits from the tag portion in that prologue tag memory.
However, Asadi teaches a preamble memory wordline driver ([0012], Asadi teaches loading word line signals in a cache memory to activate specific cells)
Asadi teaches wherein the preamble memory hit circuitry performs a comparison of preamble bits of a received address and the stored first set of bits from the tag portion in the preamble tag memory ([0033], Asadi teaches comparing lower order bits of a tag way to corresponding lower order bits in a part of a requested tag address. The lower order bits in the tag and the lower order bits in the tag ways of Asadi corresponding to the primary tag and primary tag memory of Chofleming)
Asadi teaches a prologue memory wordline driver ([0012], Asadi teaches loading word line signals in a cache memory to activate specific cells)
Asadi teaches wherein the prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored second set of bits from the tag portion in that prologue tag memory ([0033], Asadi teaches comparing higher order bits of a tag way to corresponding higher order bits in a part of a requested tag address. The higher order bits in the tag and the higher order bits in the tag ways of Asadi corresponding to the secondary tag and secondary tag memory of Chofleming)
Chofleming and Asadi are analogous art because they are from the same field of endeavor, reading parts of tags to perform a multistep cache search.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing separate preamble and prologue tag memories, as disclosed by Chofleming, with wordline drivers, comparing bits of a preamble portion of a tag with what is stored in the preamble tag memory, and comparing bits of a prologue portion of a tag with what is stored in the prologue tag memory, as disclosed by Asadi.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce read disturbance errors by eliminating a large fraction of unnecessary reads as discussed in Asadi [0033] “Since the bitwise similarity of tags in a set is likely to be reduced in lower order bits, a majority of tag ways may be discarded from the second step. By eliminating a large fraction of read operations in an exemplary tag array, read disturbance rate may be significantly reduced.”
Regarding claim 4: the combination of Chofleming/Asadi teaches all limitations of claim 1, from which claim 4 depends.
Chofleming/Asadi further teaches selection logic coupled to the one or more prologue tag memories that enables access to each of the one or more ways under control of a hit or miss signal output from the preamble memory hit circuitry of the preamble tag memory. ([0033], Asadi teaches that after lower order bits of the tags and tag ways are found to be a mismatch, the mismatched ways are disabled and the remaining ways are read and compared next)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as in Claim 1.
Regarding claim 9: the combination of Chofleming/Asadi teaches all limitations of claim 1, from which claim 9 depends.
Chofleming/Asadi further teaches each prologue tag memory of the one or more prologue tag memories is structured for storing the second set of bits and the memory data information of two or more ways ([0034], Asadi teaches that each tag way, which contains the higher order parts of the tag way bits corresponding to the prologue tag memories, may provide a physical path to a corresponding data line, which is interpreted as the memory data information of the tag way)
One of ordinary skill in the art would have been motivated to make this modification to facilitate read and write data operations from the cache memory to the data line as discussed in Asadi [0034] “Each exemplary tag way of plurality of tag ways 104 may provide a physical path to a corresponding data line in tag array 102 to perform a read or write data operation on that data line.”
Regarding claim 10: the combination of Chofleming/Asadi teaches all limitations of claim 1, from which claim 10 depends.
Chofleming/Asadi further teaches the memory subsystem further comprises a second preamble tag memory and one or more corresponding prologue tag memories for additional one or more ways of the memory subsystem ([0035], Asadi teaches that each set of a plurality of sets may be a separate place to store LSBs, ie. multiple places to store the lower order bits that correspond to the preamble tags. Asadi also teaches in [0035] that each of the LSB sets has a respective plurality of MSBs or higher order bits that correspond to the prologue tags.)
One of ordinary skill in the art would have been motivated to make this modification to enable access to a large amount of sets based on an index as discussed in Asadi [0036] “In an exemplary embodiment, decoder 106 may be coupled to plurality of tag ways 104. In an exemplary embodiment, decoder 106 may be configured to enable access to (i, k)th set 206 based on a value of index 112 of a requested address in cache memory 100. In an exemplary embodiment, index 112 may be decoded by decoder 106 to a value that may correspond to only one set in each respective plurality of sets. Based on an exemplary decoded value, decoder 106 may be coupled to a respective set to enable access to the set.”
Regarding claim 11: Chofleming teaches A method of performing tag way halting, the method comprising:
Chofleming teaches receiving, at a memory subsystem, an address for lookup; ([0019], Chofleming teaches that a cache subsystem receives a memory address)
Chofleming teaches the preamble tag memory stores a first set of bits from a tag portion of a plurality of addresses stored at the memory subsystem, wherein (Fig. 5 and [0050], Chofleming teaches that primary tags are stored in the primary tag memory 580)
Chofleming teaches bits corresponding to a plurality of different tag portions of the plurality of addresses are stored together in a same row ([0002], Chofleming teaches that cache rows are also referred to as cache sets. Furthermore, as shown in Figure 1 and [0020], the primary tags of each of the cache lines of a single set are stored within the same set, therefore, the bits of the different tag portions of the plurality of addresses are stored together in a same row.)
Chofleming teaches the prologue tag memory stores a second set of bits from the tag portion of at least some of the plurality of addresses stored at the memory subsystem and corresponding memory data information, (Fig. 5 and [0050], Chofleming teaches that secondary tags are stored in the secondary tag memory 585. Moreover, in [0027], Chofleming teaches that when secondary tags are found, there is a corresponding data made available for that cache line.)
the preamble tag memory and the one or more prologue tag memories are different tag memories having dedicated corresponding circuitry ([0050] and [0068-0069], Chofleming teaches two different primary tag memory and secondary tag memory elements with different purposes, storing different data, and being used in different steps of the process, with an example embodiment showing them being implemented on entirely different memory technologies, which is interpreted to mean that the tag memories are different tag memories with dedicated corresponding circuitry)
While Chofleming teaches matching a received primary lookup tag 535 and a received secondary tag to such tags in primary and secondary tag memory, Chofleming does not appear to explicitly disclose determining, using preamble memory hit circuitry of a preamble tag memory of the memory subsystem, a partial hit of the received address for a tag in a way, wherein the preamble memory hit circuitry performs a comparison of preamble bits of the received address and each of the stored first set of bits from the tag portion of the different tag portions of the plurality of addresses in the same row in the preamble tag memory; and for each partial hit of the received address, accessing a prologue tag memory of the memory subsystem associated with the way and determining, using prologue memory hit circuitry of the prologue tag memory, a hit of the received address for the tag in the way, wherein the prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored second set of bits from the tag portion in the prologue tag memory.
Asadi teaches determining, using preamble memory hit circuitry of a preamble tag memory of the memory subsystem, a partial hit of the received address for a tag in a way, wherein the preamble memory hit circuitry performs a comparison of preamble bits of a received address and each of the stored first set of bits from the tag portion of the different tag portions of the plurality of addresses in the preamble tag memory ([0033], Asadi teaches comparing lower order bits of a tag way to corresponding lower order bits in a part of a requested tag address to find matching and mismatching tag ways. The lower order bits in the tag and the lower order bits in the tag ways of Asadi corresponding to the primary tag and primary tag memory of Chofleming. Asadi also teaches that this is done for all tag ways in the first step.)
Asadi teaches for each partial hit of the received address, accessing a prologue tag memory of the memory subsystem associated with the way and determining, using prologue memory hit circuitry of the prologue tag memory, a hit of the received address for the tag in the way, wherein the prologue memory hit circuitry performs a comparison of prologue bits of the received address and the stored second set of bits from the tag portion in that prologue tag memory ([0033], Asadi teaches comparing higher order bits of a tag way to corresponding higher order bits in a part of a requested tag address, excluding the mismatched tag ways that were disabled. The higher order bits in the tag and the higher order bits in the tag ways of Asadi corresponding to the secondary tag and secondary tag memory of Chofleming)
Chofleming and Asadi are analogous art because they are from the same field of endeavor, reading parts of tags to perform a multistep cache search.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing separate preamble and prologue tag memories, as disclosed by Chofleming, to compare bits of a preamble portion of a tag with what is stored in the preamble tag memory to generate a first match for the tag ways, and comparing bits of a prologue portion of a tag with what is stored in the prologue tag memory to generate a full match for the address, as disclosed by Asadi.
One of ordinary skill in the art would have been motivated to make this modification in order to reduce read disturbance errors by eliminating a large fraction of unnecessary reads as discussed in Asadi [0033] “Since the bitwise similarity of tags in a set is likely to be reduced in lower order bits, a majority of tag ways may be discarded from the second step. By eliminating a large fraction of read operations in an exemplary tag array, read disturbance rate may be significantly reduced.”
Regarding claim 12: The combination of Chofleming and Asadi teach all limitations of claim 11, from which claim 12 depends.
Chofleming/Asadi further teach the determining the partial hit of the received address for the tag in the way is performed in a first cycle ([0057], Asadi teaches that the access to the sets is done in two steps, where the step of checking the LSBs for a match (ie. the partial hit) is done in a first step)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 11.
Regarding claim 13: The combination of Chofleming and Asadi teach all limitations of claim 12, from which claim 13 depends.
Chofleming/Asadi further teach the first cycle is part of a read operation of the preamble tag memory ([0015], Chofleming teaches that the receiving a cache tag and the subsequent (primary and secondary tag) lookups are part of a reading data from the cache memory.)
Regarding claim 15: The combination of Chofleming and Asadi teach all limitations of claim 12, from which claim 15 depends.
Chofleming/Asadi further teach accessing the prologue tag memory associated with the way and determining the hit of the received address for the tag in the way are performed in a subsequent cycle ([0057], Asadi teaches that accesses to the sets are done in two steps, and the step of checking the MSBs for a match (ie. the hit of the received address for the tag in the way) for looking for a target block according to the tag is done in the second step, after the first step is completed)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 11.
Regarding claim 16: The combination of Chofleming and Asadi teach all limitations of claim 15, from which claim 16 depends.
Chofleming/Asadi further teach the subsequent cycle is part of a read operation of the prologue tag memory ([0015], Chofleming teaches that the receiving a cache tag and the subsequent (primary and secondary tag) lookups are part of a reading data from the cache memory.)
Regarding claim 18: the combination of Chofleming and Asadi teaches all limitation of claim 11, from which claim 18 depends.
Chofleming/Asadi further teach the preamble bits of the tag portion contains between 3-7 bits ([0065-0066], Asadi teaches that there are cases when the number of bits compared in the first step (ie. the preamble bits) are 3 or 4)
One of ordinary skill in the art would have been motivated to make this modification in order to optimize the number of bits for the cache size used while maintaining a minimum number of read bits for gaining the read disturbance error reduction of the invention, as discussed in Asadi [0066] “As a result, the optimum value is reduced from four to three when the cache size increases by 212 times compared to a conventional size. Consequently, the increase in cache associativity does not change the optimal number of read bits in the first step, whereas a reasonable increase or decrease in the cache size can affect this number. The increase in cache size can decrease the optimal number of bits in the first step, if the cache size is increased by at least 212 times.”
Regarding claim 21: The combination of Chofleming and Asadi teach all limitations of claim 11, from which claim 21 depends.
Chofleming/Asadi further teaches for each of the stored first set of bits from the tag portion of the different tag portions of the plurality of addresses in the same row, a corresponding signal indicating a partial hit or miss is output from the preamble tag memory, wherein ([0015], Asadi teaches that the first set of comparator inputs may be connected to the lower bits of a tag, and that the comparator output may be connected to the control input of the MSB transition gates. Further, Asadi also teaches that this is done for each respective first comparator input. Therefore, a corresponding signal indicating a partial hit or miss is output from the preamble tag memories for each of the stored first set of bits from the tag portion of the different tag portions of the plurality of addresses. Combined with Chofleming’s teachings that these tags are considered for all addresses in a row, the claimed plurality of addresses in the same row are taught.)
Chofleming/Asadi further teaches accessing the prologue tag memory of the memory subsystem associated with the way in the preamble tag memory comprises: accessing the prologue tag memory under control of the corresponding signal output from the preamble tag memory. ([0015], Asadi teaches that the output signal from the first comparators either enables or disables access of the decoders for the corresponding MSB, by deactivating the transition gate. Therefore, the accessing the prologue tag under control of the corresponding signal output from the preamble tag memory is taught.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 11.
Regarding claim 22: The combination of Chofleming and Asadi teach all limitations of claim 1, from which claim 22 depends.
Chofleming/Asadi further teaches bits corresponding to a plurality of different tag portions of the plurality of addresses are stored together in a same row ([0002], Chofleming teaches that cache rows are also referred to as cache sets. Furthermore, as shown in Figure 1 and [0020], the primary tags of each of the cache lines of a single set are stored within the same set, therefore, the bits of the different tag portions of the plurality of addresses are stored together in a same row.)
Chofleming/Asadi further teaches the preamble memory hit circuitry is configured to perform a comparison of preamble bits of the received address with the bits corresponding to the plurality of different tag portions of the plurality of addresses in the same row, ([0026], Chofleming teaches that during a primary tag match, the cache management compares the primary lookup tags (from the cache tag within the received address) against the contents of the primary tag memory within a same cache line (which is within the same row).)
Chofleming/Asadi further teaches the comparison being performed in parallel for each first set of bits from the tag portion of the different tag portions of the plurality of addresses in the same row ([0040], Chofleming teaches that the computation of the primary lookup tags is done simultaneously in a parallel flow.)
Regarding claim 23: The combination of Chofleming and Asadi teach all limitations of claim 22, from which claim 23 depends.
Chofleming/Asadi further teaches for each first set of bits from the tag portion of the different tag portions of the plurality of addresses in the same row, a corresponding signal indicating a partial hit or miss is output from the preamble tag memory ([0015], Asadi teaches that the first set of comparator inputs may be connected to the lower bits of a tag, and that the comparator output may be connected to the control input of the MSB transition gates. Further, Asadi also teaches that this is done for each respective first comparator input. Therefore, a corresponding signal indicating a partial hit or miss is output from the preamble tag memories for each of the stored first set of bits from the tag portion of the different tag portions of the plurality of addresses. Combined with Chofleming’s teachings that these tags are considered for all addresses in a row, the claimed plurality of addresses in the same row are taught.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as for claim 1.
Regarding claim 24: The combination of Chofleming and Asadi teach all limitations of claim 1, from which claim 24 depends.
Chofleming/Asadi further teaches control logic configured to apply data coming into the memory subsystem to the preamble tag memory and the one or more prologue tag memories. ([0019], Chofleming teaches that for a cache access, the cache subsystem including the cache management and cache memory, including the hash functions receive a memory address, and then computes lookups for the primary lookup tags in the primary tag memory, then compares a second portion of the address to the secondary tags in the secondary tag memory. Such lookups and comparisons from the memory address being received by the subsystem are interpreted as the claimed control logic configured to apply data coming into the memory subsystem to the preamble tag memory and the prologue tag memories.)
Claims 2, 3, 19, 20 are rejected under 35 U.S.C. 103 as being unpatentable over
CHOFLEMING et al., U.S. Pub. No. 20220283948 (hereinafter “Chofleming”) in view of
Asadi et al., U.S. Pub. No. 20210201974 (hereinafter “Asadi”) further in view of
TAI et al., U.S. Pub. No. 20170116906 (hereinafter “Tai”).
Regarding claim 2: The combination of Chofleming and Asadi teach all limitations of claim 1, from which claim 2 depends.
Chofleming/Asadi further teach to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory ([0033-0034], Asadi teaches feeding the lower order part of a received tag and corresponding stored lower order bits of a tag way)
Chofleming/Asadi further teach to output a signal indicating a hit or miss of preamble bits of that corresponding way ([0033-0034], Asadi teaches to detect matching or mismatching ways as a result of the comparison)
While Asadi teaches doing the receiving and outputting a match/mismatch with a comparator circuit in [0033-0034], Chofleming/Asadi do not appear to provide any specific comparator circuit, and do not appear to explicitly disclose a set of XNOR gates; and a NAND gate that receives outputs of the set of XNOR gates to output a signal.
However, Tai teaches a set of XNOR gates that compare bits of one set of bits to corresponding bits of another set of bits (Fig. 5 and [0042], Tai teaches XNOR gates 520 that are part of a logical comparator circuit 52, which receives two sets of bits.)
Tai teaches a NAND gate that receives outputs of the set of XNOR gates to output a signal (Fig. 5 and [0042], Tai teaches a NAND gate 521 that takes in the outputs of the set of XNOR gates 520 to output a signal)
Chofleming/Asadi and Tai are analogous art because they are from the same field of endeavor, using comparators to compare two series of bits.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing comparators to determine if lower order bits match, as disclosed by Chofleming/Asadi, with the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates, as disclosed by Tai.
One of ordinary skill in the art would have recognized that the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates of Tai would be suitable for the intended purpose of a comparator that would compare two sets of bits to output whether they match, as required by Chofleming/Asadi. The specific comparator circuit of Tai would fit in the broad category of bitwise matching comparators and the combination would result in a set of XNOR gates coupled to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory; and a NAND gate that receives outputs of the set of XNOR gates to output a signal indicating a hit or miss of preamble bits of that corresponding way.
Regarding claim 3: The combination of Chofleming and Asadi teach all limitations of claim 1, from which claim 3 depends.
Chofleming/Asadi further teach to receive the prologue bits of the received address and the stored second set of bits from the tag portion of a corresponding way in the prologue tag memory ([0033-0034], Asadi teaches feeding the higher order part of a received tag and corresponding stored higher order bits of a tag way)
Chofleming/Asadi further teach to output a signal indicating a hit or miss of prologue bits of that corresponding way ([0033-0034], Asadi teaches to detect matching or mismatching ways as a result of the comparison)
While Asadi teaches doing the receiving and outputting a match/mismatch with a comparator circuit in [0033-0034], Chofleming/Asadi do not appear to provide any specific comparator circuit, and do not appear to explicitly disclose a set of XNOR gates; and a NAND gate that receives outputs of the set of XNOR gates to output a signal.
However, Tai teaches a set of XNOR gates that compare bits of one set of bits to corresponding bits of another set of bits (Fig. 5 and [0042], Tai teaches XNOR gates 520 that are part of a logical comparator circuit 52, which receives two sets of bits.)
Tai teaches a NAND gate that receives outputs of the set of XNOR gates to output a signal (Fig. 5 and [0042], Tai teaches a NAND gate 521 that takes in the outputs of the set of XNOR gates 520 to output a signal)
Chofleming/Asadi and Tai are analogous art because they are from the same field of endeavor, using comparators to compare two series of bits.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing comparators to determine if higher order bits match, as disclosed by Chofleming/Asadi, with the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates, as disclosed by Tai.
One of ordinary skill in the art would have recognized that the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates of Tai would be suitable for the intended purpose of a comparator that would compare two sets of bits to output whether they match, as required by Chofleming/Asadi. The specific comparator circuit of Tai would fit in the broad category of bitwise matching comparators and the combination would result in a set of XNOR gates coupled to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory; and a NAND gate that receives outputs of the set of XNOR gates to output a signal indicating a hit or miss of preamble bits of that corresponding way.
Regarding claim 19: The combination of Chofleming and Asadi teach all limitations of claim 11, from which claim 19 depends.
Chofleming/Asadi further teach to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory ([0033-0034], Asadi teaches feeding the lower order part of a received tag and corresponding stored lower order bits of a tag way)
Chofleming/Asadi further teach to output a signal indicating a hit or miss of preamble bits of that corresponding way ([0033-0034], Asadi teaches to detect matching or mismatching ways as a result of the comparison)
While Asadi teaches doing the receiving and outputting a match/mismatch with a comparator circuit in [0033-0034], Chofleming/Asadi do not appear to provide any specific comparator circuit, and do not appear to explicitly disclose a set of XNOR gates; and a NAND gate that receives outputs of the set of XNOR gates to output a signal.
However, Tai teaches a set of XNOR gates that compare bits of one set of bits to corresponding bits of another set of bits (Fig. 5 and [0042], Tai teaches XNOR gates 520 that are part of a logical comparator circuit 52, which receives two sets of bits.)
Tai teaches a NAND gate that receives outputs of the set of XNOR gates to output a signal (Fig. 5 and [0042], Tai teaches a NAND gate 521 that takes in the outputs of the set of XNOR gates 520 to output a signal)
Chofleming/Asadi and Tai are analogous art because they are from the same field of endeavor, using comparators to compare two series of bits.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing comparators to determine if lower order bits match, as disclosed by Chofleming/Asadi, with the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates, as disclosed by Tai.
One of ordinary skill in the art would have recognized that the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates of Tai would be suitable for the intended purpose of a comparator that would compare two sets of bits to output whether they match, as required by Chofleming/Asadi. The specific comparator circuit of Tai would fit in the broad category of bitwise matching comparators and the combination would result in a set of XNOR gates coupled to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory; and a NAND gate that receives outputs of the set of XNOR gates to output a signal indicating a hit or miss of preamble bits of that corresponding way.
Regarding claim 20: The combination of Chofleming and Asadi teach all limitations of claim 11, from which claim 20 depends.
Chofleming/Asadi further teach to receive the prologue bits of the received address and the stored second set of bits from the tag portion of a corresponding way in the prologue tag memory ([0033-0034], Asadi teaches feeding the higher order part of a received tag and corresponding stored higher order bits of a tag way)
Chofleming/Asadi further teach to output a signal indicating a hit or miss of prologue bits of that corresponding way ([0033-0034], Asadi teaches to detect matching or mismatching ways as a result of the comparison)
While Asadi teaches doing the receiving and outputting a match/mismatch with a comparator circuit in [0033-0034], Chofleming/Asadi do not appear to provide any specific comparator circuit, and do not appear to explicitly disclose a set of XNOR gates; and a NAND gate that receives outputs of the set of XNOR gates to output a signal.
However, Tai teaches a set of XNOR gates that compare bits of one set of bits to corresponding bits of another set of bits (Fig. 5 and [0042], Tai teaches XNOR gates 520 that are part of a logical comparator circuit 52, which receives two sets of bits.)
Tai teaches a NAND gate that receives outputs of the set of XNOR gates to output a signal (Fig. 5 and [0042], Tai teaches a NAND gate 521 that takes in the outputs of the set of XNOR gates 520 to output a signal)
Chofleming/Asadi and Tai are analogous art because they are from the same field of endeavor, using comparators to compare two series of bits.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory subsystem structure containing comparators to determine if higher order bits match, as disclosed by Chofleming/Asadi, with the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates, as disclosed by Tai.
One of ordinary skill in the art would have recognized that the comparator circuit with a NAND gate receiving the outputs of a set of XNOR gates of Tai would be suitable for the intended purpose of a comparator that would compare two sets of bits to output whether they match, as required by Chofleming/Asadi. The specific comparator circuit of Tai would fit in the broad category of bitwise matching comparators and the combination would result in a set of XNOR gates coupled to receive the preamble bits of the received address and the stored first set of bits from the tag portion of a corresponding way in the preamble tag memory; and a NAND gate that receives outputs of the set of XNOR gates to output a signal indicating a hit or miss of preamble bits of that corresponding way.
Claims 5, 7 are rejected under 35 U.S.C. 103 as being unpatentable over
CHOFLEMING et al., U.S. Pub. No. 20220283948 (hereinafter “Chofleming”) in view of
Asadi et al., U.S. Pub. No. 20210201974 (hereinafter “Asadi”) further in view of
Shankar et al., U.S. Pub. No. 20230195565 (hereinafter “Shankar”)
Regarding claim 5: The combination of Chofleming and Asadi teaches all limitations of claim 1, from which claim 5 depends.
While Chofleming teaches that there should be validity checking for tags in a cache, and Chofleming/Asadi teach that tags are separated into two parts and stored, Chofleming/Asadi do not appear to explicitly disclose the preamble tag memory further stores error correction code bits covering preamble bits of all ways in a row.
However, Shankar teaches tag memory further stores error correction code bits covering bits ([0027] and Fig. 3, Shankar teaches to store ECC logic for each entry of a tag RAM)
Chofleming/Asadi and Shankar are analogous art because they are from the same field of endeavor, tag memories for cache accesses.
With the separated tag memories of Chofleming and Asadi being the base device, the claimed device with the preamble tag memory storing error correction code bits covering the preamble bits could be seen as an improvement as it provides error correction capability to the preamble tag memory.
Shankar teaches a comparable device, where a tag RAM contains ECC logic for each entry of a tag RAM, wherein the tag RAM was improved in the same way as the claimed invention to provide error correction capability to the tag RAM.
One of ordinary skill in the art before the effective filing date could have applied the ECC logic to all tag RAM entries modification of Shankar to all tags of the primary tag memory of Chofleming/Asadi, which would predictably result in error correction capability to all tags of the primary tag memory, ie. the preamble tag memory further stores error correction code bits covering preamble bits of all ways in a row.
One would have been motivated to make this modification in order to improve the accuracy of the device by preventing erroneous instructions from executing, as discussed in Shankar [0053] “At 518, if an error is detected, then a memory error protocol is invoked. In this example, instruction execution of the processor is halted so that an erroneous instruction is not executed.”
Regarding claim 7: The combination of Chofleming and Asadi teaches all limitations of claim 1, from which claim 7 depends.
While Chofleming teaches that there should be validity checking for tags in a cache, and Chofleming/Asadi teach that tags are separated into two parts and stored, Chofleming/Asadi do not appear to explicitly disclose each prologue tag memory of the one or more prologue tag memories further stores error correction code bits.
However, Shankar teaches tag memory further stores error correction code bits ([0027] and Fig. 3, Shankar teaches to store ECC logic for each entry of a tag RAM)
Chofleming/Asadi and Shankar are analogous art because they are from the same field of endeavor, tag memories for cache accesses.
With the separated tag memories of Chofleming and Asadi being the base device, the claimed device with the prologue tag memories storing error correction code bits could be seen as an improvement as it provides error correction capability to the prologue tag memory.
Shankar teaches a comparable device, where a tag RAM contains ECC logic for each entry of a tag RAM, wherein the tag RAM was improved in the same way as the claimed invention to provide error correction capability to the tag RAM.
One of ordinary skill in the art before the effective filing date could have applied the ECC logic to all tag RAM entries modification of Shankar to all tags of the secondary tag memory of Chofleming/Asadi, which would predictably result in error correction capability to all tags of the secondary tag memory, ie. each prologue tag memory of the one or more prologue tag memories further stores error correction code bits.
One would have been motivated to make this modification in order to improve the accuracy of the device by preventing erroneous instructions from executing, as discussed in Shankar [0053] “At 518, if an error is detected, then a memory error protocol is invoked. In this example, instruction execution of the processor is halted so that an erroneous instruction is not executed.”
Conclusion
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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