DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/04/2025 and 05/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "The 3D-stacked semiconductor device" in line 1. There is insufficient antecedent basis for this limitation in the claim. The examiner suggests changing to “The semiconductor device”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 11-15 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHILIANG et al. (US Patent Appl. Pub. No. 2022/0102520 A1).
[Re claim 1] SHILIANG discloses the semiconductor device comprising: a 1st source/drain pattern (114 right side); a 2nd source/drain pattern (114 left side); an isolation wall (111 and 112) between the 1st source/drain pattern and the 2nd source/drain pattern; a 1st active contact (1012 right side) on the 1st source/drain pattern; and a 2nd active contact (1012 left side) on the 2nd source/drain pattern, wherein the 1st active contact (1012 right side) contacts a 1st side surface of the isolation wall (right side of 112 and 122), and wherein the 2nd active contact (1012 left side) contacts a 2nd side surface of the isolation wall (left side of 111 and 112), opposite to the 1st sidewall (see figure 15-21 and paragraph [0108]-[0133]).
[Re claim 2] SHILIANG discloses the semiconductor device wherein the 1st active contact (1012 right side) and the 2nd active contact (1012 left side) are connected (connected by gate structure 121) over a top surface of the isolation wall (see figure 19 and paragraph [0126]-[0130]).
[Re claim 3] SHILIANG discloses the semiconductor device further comprising: a 1st channel structure (1012 right side) on the 1st source/drain pattern; and a 2nd channel structure (1012 left side) on the 2nd source/drain pattern, wherein the 1st channel structure contacts the 1st side surface of the isolation wall, and the 2nd channel structure contacts the 2nd side surface of the isolation wall (see figure 15-21 and paragraph [0108]-[0133]).
[Re claim 4] SHILIANG discloses the semiconductor device wherein each of the 1st channel structure and the 2nd channel structure comprises a plurality of vertically stacked active layers (see figure 18).
[Re claim 11] SHILIANG discloses the semiconductor device comprising: a 1st source/drain pattern (right side of 114); a 1st active contact (right side of 1012) on the 1st source/drain pattern; and an isolation wall (122 and 112) contacting the 1st active contact (see figure 15-21 and paragraph [0108]-[0133]).
[Re claim 12] SHILIANG discloses the semiconductor device wherein the 1st active contact (right side of 1012) contacts a side surface of the isolation wall (right side of 112 and 122) (see figure 18).
[Re claim 13] SHILIANG discloses the semiconductor device wherein the 1st source/drain pattern (right side of 114) contacts the isolation wall (right side of 111 and 112) (see figure 21).
[Re claim 14] SHILIANG discloses the semiconductor device further comprising a 1st channel structure (right side of 1012) on the 1st source/drain pattern, wherein the 1st channel structure and the 1st source/drain pattern contact the isolation wall (see figure 18 and 21).
[Re claim 15] SHILIANG discloses the semiconductor device further comprising: a 2nd source/drain pattern (left side of 114); and a 2nd active contact (left side of 1012), wherein the 2nd active contact contacts the isolation wall (see figure 15-21 and paragraph [0108]-[0133]).
[Re claim 18] SHILIANG discloses the method of manufacturing a semiconductor device, the method comprising: forming a channel structure (1012) on a substrate; forming a recess (106) penetrating through the channel structure to divide the channel structure into a 1st channel structure and a 2nd channel structure; forming an isolation wall (111 and 112) in the recess; forming a 1st source/drain pattern (right side of 114) on the 1st channel structure; and forming a 1st active contact contacting the isolation wall and the 1st source/drain pattern (see figure 5-14 and paragraph [0021]-[0085]).
[Re claim 19] SHILIANG discloses the method further comprising: forming a 2nd source/drain pattern (left side of 114) on the 2nd channel structure (left side of 1012); and forming a 2nd active contact contacting the isolation wall and the 2nd source/drain pattern (see figure 8 and 14).
[Re claim 20] SHILIANG discloses the method wherein the 1st source/drain pattern (right side of 114) is formed to contact the 1st active contact (right side of 1012) (see figure 8 and 14).
Allowable Subject Matter
Claim 5-10 and 16-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817
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