DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/28/2026 has been entered.
Status of Application
Claims 21 and 23-35 are pending in the present application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 21, 26 and 31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The examiner acknowledges applicant’s remarks regarding the inclusion of subject matter indicated as allowable [remarks, pp. 8-9], however the examiner notes that applicant has also deleted claim language in regard to the “message header” and omitted “two dimensional (2D) memory surface” from the independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23 and 24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 23 and 24 depend on claim 22, however claim 22 has been cancelled. Appropriate correction is required. The examiner will interpret claims 23 and 24 to depend on claim 21.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 26, and 31 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2, 11, and 17, respectively of U.S. Patent No. 12,039,000 B2, in view of Bradford et al (hereinafter Bradford), US 20190042248 A1.
The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 12,039,000 B2
Claim 21. An apparatus comprising:
processing circuitry to: examine a message descriptor associated with an instruction to determine a type of matrix layout manipulation operation that is to be executed;
retrieve one or more blocks associated with matrix data from a memory based on parameters associated with the instruction, wherein the parameters define a memory surface that is to be retrieved and comprises an array length attribute indicating a quantity of block to be retrieved from the memory;
and
store the one or more blocks associated with the matrix data using a set of registers.
Claim 1. An apparatus comprising:
accelerator hardware to execute an instruction to:
examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, wherein a parameter comprises an array length attribute that indicates a quantity of memory blocks to retrieve from memory;
retrieve one or more blocks of matrix data based on the plurality of parameters; and
store the one or more blocks of the matrix data.
Claim 2. The apparatus of claim 1, wherein the accelerator hardware further executes the instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operations that is to be executed.
‘000 does not explicitly disclose the storing using a set of registers.
However, Bradford discloses storing using a set of registers [see fig. 3A and paragraph 39, where the blocks are stored in Load Buffer; “Execution circuitry 110 also includes load buffer 114, which in some embodiments is an array of registers”; fig. 3A also shows storing the blocks in destination matrix 308; paragraph 38 disclosing a matrix to be stored in a collection of registers, locations in memory (e.g., as strided rows), or in other storage accessible to execution circuitry)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bradford in the apparatus of ‘000 to implement, the storing using a set of registers, in order avoid the slowdown and code size that would be associated with a software implementation, and provide more flexible and expandable transpose circuits [Bradford, paragraph 37].
Claim 27 and 32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 17, respectively, of U.S. Patent No. 12,039,000 B2, in view of Bradford.
Claims 24 and 29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4 and 13, respectively, of U.S. Patent No. 12,039,000 B2, in view of Bradford.
Claims 21, 26, and 31 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 16, respectively, of U.S. Patent No. 11,593,454 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because every claim limitation in the application under examination is recited in the conflicting reference patent claims.
The differences between the claims are highlighted below by italicizing all limitations that differ and bolding limitations that conflict.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 11,593,454 B2
Claim 21. An apparatus comprising:
processing circuitry to: examine a message descriptor associated with an instruction to determine a type of matrix layout manipulation operation that is to be executed;
retrieve one or more blocks associated with matrix data from a memory based on parameters associated with the instruction, wherein the parameters define a memory surface that is to be retrieved and comprises an array length attribute indicating a quantity of block to be retrieved from the memory; and
store the one or more blocks associated with the matrix data using a set of registers.
Claim 1. An apparatus to facilitate machine learning matrix processing, comprising:
a memory to store matrix data;
one or more processors to execute an instruction to:
examine a message descriptor included in the instruction to determine a first of a plurality of types of matrix layout manipulation operations that is to be executed;
examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, wherein the parameters comprise an array length attribute indicating a quantity of 2D memory blocks to retrieve from memory;
retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters; and
a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
Claims 27 and 32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 16, respectively, of U.S. Patent No. 11,593,454 B2.
Claims 23 and 28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4 and 12, respectively, of U.S. Patent No. 11,593,454 B2.
Claims 24 and 29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 and 15, respectively, of U.S. Patent No. 11,593,454 B2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21, 24-26, 30-31, and 33-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al (hereinafter Luo), US 20200034306 A1, in view of Bannon et al (hereinafter Bannon), US 20190250830 A1, and further in view of Bradford et al (hereinafter Bradford), US 20190042248 A1.
Referring to claims 21, 26, and 31, taking claim 21 as exemplary, Luo discloses an apparatus comprising:
processing circuitry [fig. 6A, element 502] to:
examine a message descriptor associated with an instruction to determine a type of matrix layout manipulation operation that is to be executed [paragraphs 34-35, 47, “The set of instructions may be a command with beginning ‘Read’ or ‘Write’”; An instruction of the set of instructions may be structured as: ‘COMMAND (P, M, N, L)…M may indicate a type of memory command; such as…M=3 being for a submatrix memory command; “As an example of an instruction, a row memory command to read a row of stored memory may be structured as: READ (P, 0, 10); which indicates that the data is to be read at starting address P along a row of the stored memory for 10 data points. As another example, a submatrix memory command to write a submatrix of stored memory may be structured as: WRITE (P, 3, 5, 5); which indicates that data is to be written at a starting address P in a 5×5 submatrix”; hence Luo discloses a 2D block read operation when specifying a READ with M=3, where READ and M are equivalent to the message descriptor; Luo also discloses a read command that may be a diagonal memory command, as part of a series of tensor operations, to read a diagonal of memory units 540. The diagonal read command may comprise a diagonal memory operation, a starting address for the diagonal memory operation, and a dimension of a tensor for the diagonal memory operation];
retrieve one or more blocks associated with matrix data from a memory based on parameters associated with the instruction [paragraphs 34-35, 47, reading/retrieving submatrix according to COMMAND (P, M, N, L), specifically parameters N and L (N x L submatrix) for retrieving one block; see fig. 6A and reading/retrieving from 540];
store the one or more blocks associated with the matrix data [fig. 6A, paragraph 48, the memory controller 510 reads the first data from the memory units 540…At (4), that read data…is written to the data buffer 530].
Luo does not explicitly disclose wherein the parameters define a memory surface that is to be retrieved and comprises an array length attribute indicating a quantity of block to be retrieved from the memory.
However, Bannon discloses wherein the parameters define a memory surface that is to be retrieved [paragraph 41, “In embodiments, parameters, may comprise convolution parameters, such convolution block size, stride, and number of channels such that a preferred block length is identified for storing data in memory”; the convolution block size defining a memory surface that is to be retrieved] and comprises an array length attribute indicating a quantity of block to be retrieved from the memory [paragraphs 43-44, “a block count, representative of a number of data blocks to be retrieved from memory, is calculated”; “Finally, at step 408, data blocks are retrieved from memory”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bannon in the apparatus of the modified Luo to implement, wherein the parameters define a memory surface that is to be retrieved and comprises an array length attribute indicating a quantity of block to be retrieved from the memory, in order to allow for efficient memory management that reduces data latency and, thus, data management cost and power consumption [Bannon, paragraph 9].
The modified Luo does not explicitly disclose storing using a set of registers.
However, Bradford discloses storing using a set of registers [fig. 3A, paragraph 39, [see fig. 3A and paragraph 39, where the blocks are stored in Load Buffer; “Execution circuitry 110 also includes load buffer 114, which in some embodiments is an array of registers’”; fig. 3A also shows storing in destination matrix 308; paragraph 38 disclosing a matrix to be stored in a collection of registers, locations in memory (e.g., as strided rows), or in other storage accessible to execution circuitry)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bradford in the apparatus of the modified Luo to implement, storing using a set of registers, in order to efficiently transpose data within a matrix with a single instruction [Bradford, paragraph 35].
Referring to claim 24, the modified Luo discloses the apparatus of claim 22, wherein the processing circuitry is further to perform a transpose operation on the one or more blocks and store the transposed matrix using the set of registers [Bradford, fig. 3A, Matrix Transpose Instruction 301 and seeing storing in 308].
Referring to claims 25, 30, and 35, taking claim 30 as exemplary, the modified Luo discloses the apparatus of claim 21, wherein the processing circuitry is coupled to a memory [Luo, fig. 3, elements 530, 540], the processing circuitry comprising one or more of graphics processing circuitry or application processing circuitry [Luo, paragraph 83, application-specific integrated circuit (ASIC)].
Referring to claim 33, the modified Luo discloses the non-transitory computer- readable medium of claim 31, wherein the parameters comprise attributes defining one or more of a width, a height [Luo, paragraphs 34-35, 47, reading/retrieving submatrix according to COMMAND (P, M, N, L), specifically parameters N and L (N X L submatrix) for retrieving one block; see fig. 6A and reading/retrieving from 540], or a pitch associated with one or more blocks of the quantity of blocks, wherein the message description to indicate a 2D block read [Luo, paragraphs 34-35, 47] with transpose operation to be executed [Bradford, fig. 3A, Matrix Transpose Instruction 301].
Referring to claim 34, the modified Luo discloses the non-transitory computer- readable medium of claim 31, wherein the operations further comprise performing a transpose operation on the one or more blocks and storing the transposed matrix using the set of registers [Bradford, fig. 3A, Matrix Transpose Instruction 301 and seeing storing in 308].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/Primary Examiner, Art Unit 2181
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