Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The IDS filed including only the Texas Instruments internal document has not been considered since its not in compliance with 37 CFR 1.98. The internal document does not appear to be a publication and is not dated.
Claim Objections
3. Claim 8 is objected to because of the following informalities: In claim 8, on line 1, applicant refers to “a first capacitor”. However, applicant already refers to “a first capacitor” on line 20 of claim 1. Even though the drawing reference to each clearly delineates them, it would read better if they were not named the same thing. Appropriate correction is required.
Claim Rejections - 35 USC § 112
4. Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, on line 14, “the first input terminal (302)” lacks antecedent basis. In claim 2, on line 4, “the second input terminal (304)” lacks antecedent basis. In claim 6, on line 5, “the second input terminal (304)” lacks antecedent basis.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Gu US 12494751 B2 in view of Byung-du KR-102644623-B3.
7. Consider claim 1. Gu (fig 1) teaches a transmitter circuit (11) comprising: a first transistor (M5) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first transistor coupled to ground and the control terminal of the first transistor (M5) coupled to a first voltage (Vref); a second transistor (M6) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second transistor (M6) coupled to the first current terminal of the first transistor (M5), the control terminal of the second transistor (M6) coupled to a second voltage (VB2), and the first current terminal of the second transistor (M6) coupled to a first output terminal (out-); a third transistor (M1) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the third transistor (M2) coupled to a voltage supply (Vdd) and the control terminal of the third transistor (M2) coupled to a third voltage (Vdd through capacitor Cg) and coupled to the first input terminal (in+); a fourth transistor (M2) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the fourth transistor (M2) coupled to the first current terminal of the third transistor (M1), the control terminal of the fourth transistor (M2) coupled to a fourth voltage (Vdd through Ce), and the first current terminal of the fourth transistor (M2) coupled to the first output terminal (344) and a first capacitor (Cb) coupled between the first input terminal (in+) and the control terminal of the first TFT (308P). Gu using CMOS transistors but fails to teach the transmitter circuit made of thin-film transistors. However, Byuong-du teaches the advantages of using stacked thin-film transistors in his transmitter circuit (…The first PMOS member 110, the second PMOS member 210, the third PMOS member 310, the 2a NMOS member 220, and the 3a NMOS member 320 are thin film oxide transistor types...). It would have been obvious, before the effective date to substitute the thin-film transistors taught by Byuong-du for the CMOS in Gu in order to save manufacturing costs.
8. Regarding claim 2. Gu teaches (fig 1) a fifth transistor (M7) having a control terminal, a first current terminal, and a second current terminal, the second current terminal coupled to the voltage supply (Vref through Rf), the control terminal of the fifth transistor (M7) coupled to the second input terminal (In-), and the first current terminal of the third transistor (M1) coupled to the first current terminal of the second transistor (M2) and the first output terminal (out-).
9. Regarding claim 3. Gu teaches further including a second capacitor (Ca) coupled between the first input terminal (in+) and the control terminal of the third transistor (M1).
10. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Gu US 12494751 B2 in view of Byung-du KR-102644623-B3 further in view of Kim et al US 20240054959 A1.
11. Regarding claims 4 and 5. Gu fails to teach an inverter buffer (i.e. inverter) coupled between the first input terminal (in+) and the first capacitor (Cb). However, such is known in the art as taught by Kim et al. (see fig 2). It would have been obvious, to use an inverter as taught by Kim et al in the location called for between the first input terminal (in+) and the first capacitor (Cb) of Gu in order to supply negative voltage to (in-) thus saving circuit space.
Claim Objections
12. Claims 6-8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Regarding claim 6. The prior art of record fail to teach or make obvious the specific circuit including the limitations described and connected as italicized below including: a fifth TFT (308N) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the fifth TFT (308N) coupled to ground and the control terminal of the fifth TFT (308N) coupled to a fifth voltage and coupled to the second input terminal (304); and a sixth TFT (312N) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the sixth TFT (312N) coupled to the first current terminal of the fifth TFT (308N), the control terminal of the sixth TFT (312N) coupled to a sixth voltage, and the first current terminal of the sixth TFT (312N) coupled to a second input terminal (304).
Regarding claim 7. The prior art of record fail to teach or make obvious the specific circuit including the limitations described and connected as italicized below including a fifth TFT (represented in 320P) having a control terminal, a first current terminal, and a second current terminal, the control terminal of the fifth TFT coupled to a fifth voltage, the first current terminal of the fifth TFT coupled to the first output terminal (344), and the second current terminal of the fifth TFT coupled to the first current terminal of the second TFT (312P); and a sixth TFT (represented 340P) having a control terminal, a first current terminal, and a second current terminal, the control terminal of the sixth TFT coupled to a bias voltage, the first current terminal of the sixth TFT coupled to the second current terminal of the fourth TFT (332P), and the second current terminal of the sixth TFT coupled to the first output terminal (344).
Regarding claim 8. The prior art of record fail to teach or make obvious the specific circuit including the limitations described and connected as italicized below including: a resistor (307P) having a first terminal and a second terminal, the first terminal of the resistor (307P) coupled to the first voltage and the second terminal of the resistor (307P) coupled to the control terminal of the first TFT (308P); a first capacitor (318P) having a first terminal and a second terminal, the first terminal of the first capacitor (318P) coupled to the second current terminal of the second TFT (312P); and a second capacitor (316P) having a first terminal and a second terminal, the first terminal of the second capacitor (316P) coupled to the second terminal of the resistor (314P) and the second terminal of the first capacitor (318P), the second terminal of the second capacitor (316P) coupled to the ground terminal.
13. Claims 9-20 are allowed.
Regarding claim 9. The prior art of record fail to teach or make obvious the specific circuit including the limitations described and connected as italicized below including: a receiver circuit (214) ; a transmitter (232) including: a supply terminal; a first input terminal (302) coupled to the receiver circuit (214) ; a first output terminal (344); a ground terminal; a first thin-film transistor (TFT) (308P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first TFT (308P) coupled to the supply terminal and the control terminal of the first TFT (308P) coupled to a first voltage; a second TFT (312P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second TFT (312P) coupled to the first current terminal of the first TFT (308P), the control terminal of the second TFT (312P) coupled to a second voltage, and the first current terminal of the second TFT (312P) coupled to the first output terminal (344); a third TFT (328P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the third TFT (328P) coupled to the ground terminal and the control terminal of the third TFT (328P) coupled to a third bias voltage and coupled to the first input terminal (302); a fourth TFT (332P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the fourth TFT (332P) coupled to the first current terminal of the third TFT (328P), the control terminal of the fourth TFT (332P) coupled to a fourth voltage, and the first current terminal of the fourth TFT (332P) coupled to the first output terminal (344); a first capacitor (309P) coupled between the first input terminal (302) and the control terminal of the first TFT (308P); and a second capacitor (327P) coupled between the first input terminal (302) and the control terminal of the third TFT (328P). Dependent claims 10-14 are allowable since they depend upon claim 9.
Regarding claim 15, The prior art of record fail to teach or make obvious the specific circuit including the limitations described and connected as italicized below including: a bias circuit (350) including: a first diode connected transistor (362) to supply a first voltage; and a second diode connected transistor (360) coupled to the first diode connected transistor (362), the second diode connected transistor (360) to supply a second voltage; a third diode connected transistor (354) to supply a third voltage; and a fourth diode connected transistor (352) coupled to the third diode connected transistor (354), the fourth diode connected transistor (352) to supply a fourth voltage; and a transmitter (300) including: a supply terminal; a first input terminal (302); a first output terminal (344); a ground terminal; a first thin-film transistor (TFT) (308P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first TFT (308P) coupled to the supply terminal and the control terminal of the first TFT (308P) coupled to the first voltage and coupled to the first input terminal (302); a second TFT (312P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second TFT (312P) coupled to the first current terminal of the first TFT (308P), the control terminal of the second TFT (312P) coupled to the second voltage, and the first current terminal of the second TFT (312P) coupled to the first output terminal (344); a third TFT (328P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the third TFT (328P) coupled to the ground terminal and the control terminal of the third TFT (328P) coupled to the bias voltage and coupled to the first input terminal (302); and a fourth TFT (332P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the fourth TFT (332P) coupled to the first current terminal of the third TFT (328P), the control terminal of the fourth TFT (332P) coupled to the fourth voltage, and the first current terminal of the fourth TFT (332P) coupled to the first output terminal (344). Dependent claims 16-20 are allowable since they depend upon claim 9.
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Poon et al US 12160256 B2 teaches (fig 1) serializer/deserializer (SerDes) circuit having a SerDes transmitter and a SerDes receiver.
Yu US 8614700 B2 teaches a voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CURTIS A KUNTZ whose telephone number is (571)272-7499. The examiner can normally be reached M-Th from 530am to 330pm and Fri from 530am to 10am.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew D Anderson, can be reached at telephone number 5712724177. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center to authorized users only. Should you have questions about access to the USPTO patent electronic filing system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice.
/CURTIS A KUNTZ/Primary examiner, Art Unit 2646
Prosecution Insights