/DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/30/2026 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 08/30/2026. Claims 1-17 are pending. Claims 7 and 11-15 are amended.
The amendment to the Drawings filed 08/30/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the SFACT shown in Fig. 5 being 2-way set associative, each way having a source tag and destination, and the specific example of the Branch instruction PC and Destination branch target, were not found to be described in the original disclosure.
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
The drawings are objected to for the follow reasons:
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, a reorder buffer (as described in claim 3) and a coarse-grained set of locations augmented with a bit mask and associated with the one or more virtual memory locations (as described in claim 6) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant's arguments filed 08/30/2026 have been fully considered but they are not persuasive.
On page 11 of the Remarks, Applicant argues that the two-way association shown in Fig. 5 is well known in the art and has ample bases in the specification as filed. However, this argument is not persuasive. While the specification supports a 2-way set associative SMACT, the specification does not support a 2-way set associative SFACT. Further, 2-way association being well known in general is not enough to support the SFACT specifically being 2-way set associative.
On page 13 of the Remarks, Applicant argues, with respect to claims 1 and 9, that “Lee is not at all related to speculative execution but rather it is concerned with valid branch instruction execution.” However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The rejection of claims 1 and 9 modify Lee to support speculative control flow instructions as taught by Solomatnikov. Thus, while Lee alone may not be directed to speculative execution explicitly, the combination of Lee and Solomatnikov is directed to speculative execution.
On pages 13-17 of the Remarks, Applicant alleges that the LUT of Lee is under control of the operating system and not corruptible, is set up once and never modified, is a static one-time written-to table loaded by the programmer, not to be altered, does not change, and is provided as part of the compilation of the program. However, this argument is not persuasive because there does not appear to be any specific disclosure in Lee of the LUT being provided by the compiler or set up once and never modified. Applicant further cites the lack of disclosure of updating the LUT as evidence for the LUT being static, however, just because Lee is silent on updating the LUT does not mean that the LUT cannot be modified to be updated.
On page 17 of the Remarks, Applicant argues why it would make sense for the tables of Lee to be static. However, this argument is not persuasive because Lee never discloses that it’s tables are static, Lee is concerned with preventing a branch instruction which is loaded to perform instructions not adjacent to the presently loaded instruction to prevent damage due to a computer virus or hacker, see [0040], and Lee does this by using the LUT to verify whether the branches are verified or not. While there may be reason for making the LUT static (i.e., to prevent a hacker from additionally making changes to the LUT) there are also reasons why the LUT may not be static, for example, the hacker may not anticipate there being a LUT that verifies the malicious branches, in which case the hacker wouldn’t know to additionally access the LUT to make changes, and a dynamic LUT would allow for preventing speculative attacks (as taught by Solomatnikov).
On pages 18-19 of the Remarks, Applicant argues that claims 1 and 9 are directed to updating the memory tables at runtime whereas Lee’s LUT is uploaded as part of compiling the program and is to be a constant table. However, this argument is not persuasive. As explained above, there is no disclosure in Lee that the LUT is uploaded as part of compiling the program or that the LUT must be a constant table. Thus, while Lee may be silent with respect to updating the LUT, the rejection modifies Lee to update its LUT in view of Solomatnikov, which teaches updating an entry to be activated is the control flow instruction is validated, see [0057]. Examiner notes that Applicant’s arguments only attack the primary reference (Lee) and do not consider how the combination of references would arrive at the claimed invention. Further, Examiner notes that the limitations in claims 1 and 9 directed to updating the tables are contingent limitations not required under BRI of a method claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2008/0256346 in view of Solomatnikov US 2019/0286443, Von Praun US 2009/0177871, and Hennessy “Computer Architecture, A Quantitative Approach”.
Regarding claim 1, Lee teaches:
1. A method of verifying authenticity of a speculative control-flow instruction, comprising:
receiving a new source-destination pair (NEW-PAIR), wherein the source represents a control-flow instruction identified by an associated source memory location where the control-flow instruction is located and the destination represents an associated destination memory location where a next instruction to be executed is located ([0057]-[0059]: the LUT receives the branch instruction address (i.e., an associated source memory location where the control-flow instruction is located) and the branch target address (i.e., a destination/associated destination memory location where a next instruction to be executed is located));
checking the NEW-PAIR against one or more memory tables each having memory source-destination pairs (OLD-PAIRS) ([0057]-[0059]: the combination of the branch instruction address and the branch target address (i.e., the pair) is checked against the LUT, which has memory source-destination pairs, see Fig. 3 );
if the NEW-PAIR exists in the one or more memory tables, fetching the destination of the NEW-PAIR ([0045] and [0057]: if the pair exists in the LUT, the branch instruction is valid and is executed, which would involve fetching the instruction at the destination of the branch);
if the NEW-PAIR does not exist in the one or more memory tables, i) waiting until the speculation of the source of the NEW-PAIR has cleared as being non-speculative or one or more program counter clock cycles later, ii) updating the one or more memory tables, wherein the updating is associated with inclusion of the NEW-PAIR as a new authentic pair, and iii) fetching an instruction of the non-speculative destination of the NEW-PAIR (this contingent limitation is not required under BRI of a method claim since it is contingent on the NEW-PAIR not existing in the tables, which the claim does not require; nonetheless, Lee [0045] and [0057] teaches that if the pair does not exist in the LUT, the branch is invalid and the execution unit does not execute the branch instruction, i.e., the source is nullified); and
if the speculation of the source of the NEW-PAIR does not clear as non-speculative, then the source of the NEW-PAIR is nullified (this contingent limitation is not required under BRI of a method claim since it is contingent on the speculation of the source of the NEW-PAIR not clearing as non-speculative, which the claim does not require; nonetheless, Lee [0045] and [0057] teaches that if the pair does not exist in the LUT, the branch is invalid and the execution unit does not execute the branch instruction, i.e., the source is nullified).
Lee does not teach:
receiving a new speculative source-destination pair (NEW-PAIR), wherein the source represents a speculative control-flow instruction identified by an associated source virtual memory location where the speculative control-flow instruction is located and the destination represents an associated destination virtual memory location where a next instruction to be executed is located, wherein the speculative control-flow instruction represents either a non-control-flow instruction mis-speculated as a control-flow instruction or an actual control-flow instruction;
the one or more memory tables each having memory source-destination pairs (OLD-PAIRS) associated with previous combinations of source-destination pairs that have successfully cleared as non-speculative source-destination pairs upon reaching commit in prior executions
However, Solomatnikov teaches:
receiving a speculative control flow instruction, wherein the speculative control-flow instruction represents either a non-control-flow instruction mis-speculated as a control-flow instruction or an actual control-flow instruction ([0054]-[0055] describes that speculative execution may continue at step 530 or may be constrained at 540 based on the entry for the control flow instruction being activated, which indicates that the control flow instruction received for steps 510-520 is a speculative instruction);
checking if the speculative control flow instruction is associated with an activated entry (analogous to Lee checking if a pair is in the LUT), see [0053], the activated entry being associated a previously validated control flow instruction ([0057]: an entry is activated if the prediction is validated, see also [0019] describing that the entry may be activated after the first time the control flow instruction is executed or the first time a prediction based on the entry is validated);
Examiner notes that, while not required by the claim, Solomatnikov further teaches: if the speculative control flow instruction is not associated with an activated entry (analogous to a branch not being in the LUT in Lee), i) waiting until the speculation of the source has cleared as being non-speculative or one or more program counter clock cycles later ([0056]: the control flow instruction may execute without speculation at step 542, that is, step 542 waits until speculation of the control flow instruction clears as being non-speculative), ii) updating the entry, wherein the updating is associated with inclusion of the PAIR as a new authentic pair ([0057]: step 548 activates the entry if the control flow instruction is validated), and iii) fetching the instruction of the non-speculative destination ([0056]: continuing execution of the control flow instruction without speculative execution indicates that the instruction of the non-speculative destination of the control flow instruction will be fetched);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee to support speculative control flow instructions as taught by Solomatnikov such that the combination would check speculative control flow instructions against the LUT, which would include previous combinations of source and destination addresses that have been validated/cleared as non-speculative, and if the pair does not exist in the LUT, the combination would wait for the control flow instruction to be non-speculatively executed (i.e., clear as non-speculative), update the LUT to include the new PAIR, and fetch the non-speculative destination of the PAIR (when the pair is executed non-speculatively), and if the speculation does not clear as non-speculative, then the branch would be verified as invalid/nullified. One of ordinary skill in the art would have been motivated to make this modification to support speculative execution, which would enable the processor to achieve higher performance by avoiding pipeline delays, while preventing or mitigating side-channel attacks (Solomatnikov [0020] and [0054]).
While Solomatnikov teaches determining the results of a control flow instruction before determining if the prediction for the control flow instruction is validated, see [0056]-[0057], The combination of Lee and Solomatnikov does not explicitly teach the validated control flow instruction successfully clearing as non-speculative upon reaching commit in prior executions; or an associated source virtual memory location and an associated destination virtual memory location.
However, Von Praun teaches speculative computation that becomes non-speculative at the time of commit, see [0048].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the combination of Lee in view of Solomotnikov to validate control flow instructions that successfully clear as non-speculative upon reaching commit as taught by Von Praun such that the LUT of the combination would include previous combinations of source and destination addresses that have been validated/cleared as non-speculative upon reaching commit in previous executions. One of ordinary skill in the art would have been motivated to make this modification to ensure that the control flow instructions are validated upon reaching commit, which would strengthen the validation of the control flow instructions (as results determined at commit would be more valid that results that have not reached commit).
The combination of Lee, Solomatnikov, and Von Praun does not teach:
an associated source virtual memory location and an associated destination virtual memory location.
However, Hennessy teaches using virtual memory mapped to physical memory, see B-41.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee in view of Solomatnikov to use virtual memory mapped to physical memory as taught by Hennessey such that the addresses used by the combination, including the source and destination memory locations associated with the pairs, would be virtual addresses. One of ordinary skill in the art would have been motivated to make this modification to relieve programmers of the burden of managing program accesses to physical memory and to simplify loading a program for execution (Hennessy B-41-B-42).
Regarding claim 2, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
2. The method of claim 1, wherein the one or more memory tables includes a Speculative instruction Fetch Access Control Table (SFACT) housing authentic source-destination pairs (the LUT of the combination stores/houses validated/authentic source-destination pairs (as Solomatnikov teaches validating/authenticating the control flow instruction at step 545 of Fig. 5) and is a SFACT in the sense that it controls fetch access of speculative control flow instructions by ensuring that the speculative control flow instruction is verified before its target is fetched (otherwise the control flow instruction is invalidated/not executed, see Lee [0045])).
Regarding claim 2, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
3. The method of claim 1, wherein the speculation of the source of the NEW-PAIR is cleared as non-speculative when the source reaches the head of a Reorder Buffer (this contingent limitation is not required under BRI of a method claim since it is contingent on the source reaching the head of a Reorder Buffer, which the claim does not require).
Regarding claim 4, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
4. The method of claim 1, wherein the step of checking the NEW-PAIR against one or more memory tables includes using the source of the NEW-PAIR to look up previous combinations of source-destination pairs that have successfully cleared as non- speculative source-destination pairs (OLD-PAIRS) (Lee [0059] teaches checking if the combination of the branch instruction address and the branch target address are in the LUT, which indicates that both the branch instruction address (i.e., the source) and the branch target address are used to look up the LUT for previous combinations of pairs that successfully cleared as non-speculative (in the combination)).
Regarding claim 5, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
5. The method of claim 1, wherein the step of checking the NEW-PAIR against one or more memory tables includes using the destination of the NEW-PAIR to look up previous combinations of source-destination pairs that have successfully cleared as non- speculative source-destination pairs (OLD-PAIRS) (Lee [0059] teaches checking if the combination of the branch instruction address and the branch target address are in the LUT, which indicates that both the branch instruction address and the branch target address (i.e., the destination) are used to look up the LUT for previous combinations of pairs that successfully cleared as non-speculative (in the combination)).
Regarding claim 7, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
7. The method of claim 1, wherein each of the one or more memory tables associated with the previous combinations of source-destination pairs that have successfully cleared as non-speculative source-destination pairs (OLD PAIRS) are amended via hardware or software control (the combination updates/amends entries in the LUT with pairs that have cleared as non-speculative (see Solomatnikow Fig. 5 teaching activating/updating an entry at step 548 once the prediction is validated at step 545), which is done via hardware or software control since any step in a processor occurs under hardware or software control).
Regarding claim 8, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
8. The method of claim 1, wherein the source of the NEW-PAIR or the OLD-PAIRs is i) a complete instruction or ii) a micro-operation included in a complex instruction comprising a plurality of micro- operations (Lee [0057]: the source is a branch instruction, which is a complete instruction).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2008/0256346 in view of Solomatnikov US 2019/0286443, Von Praun US 2009/0177871, Hennessy “Computer Architecture, A Quantitative Approach”, and Zhang US 2008/0263315.
Regarding claim 6, Lee in view of Solomatnikov, Von Praun, and Hennessy teaches:
6. The method of claim 1,
Lee in view of Solomatnikov, Von Praun, and Hennessy does not teach:
wherein the one or more virtual memory locations associated with each of the source and the destination of the NEW-PAIR or the OLD-PAIRs are represented as a coarse-grained set of locations augmented with a bit mask to identify one or more finer-grain locations contained within the coarse-grained set.
However, Zhang teaches a segment/mask addressing mode which divides memory locations into segments and identifies locations in a segment using a mask, see [0022]-[0026]. Examiner notes that while the description may be directed to register addressing, the teaching apply more broadly to memory addressing.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the LUT of Lee in view of Solomatnikov, Von Praun, and Hennessy to use the segment/mask address taught by Zhang such that the combination would represent the source and destinations as segments (i.e., a course-grained set of locations) augmented with a mask (i.e., a bit mask to identify finer-grain locations). One of ordinary skill in the art would have been motivated to make this modification to improve addressing efficiency (Zhang [0022] and [0027]).
Claims 9-13, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2008/0256346 in view of Solomatnikov US 2019/0286443.
Regarding claim 9, Lee teaches:
9. A method of verifying authenticity of a speculative control-flow instruction, comprising:
receiving a new source-destination pair (NEW-PAIR), wherein the source represents a control-flow instruction identified by an associated physical source memory location where the control-flow instruction is located and the destination represents an associated destination physical memory location where a next instruction to be executed is located ([0057]-[0059]: the LUT receives the branch instruction address (i.e., an associated source physical memory location where the control-flow instruction is located) and the branch target address (i.e., a destination/associated destination physical memory location where a next instruction to be executed is located));
checking the NEW-PAIR against one or more memory tables each having memory source-destination pairs (OLD-PAIRS) ([0057]-[0059]: the combination of the branch instruction address and the branch target address (i.e., the pair) is checked against the LUT, which has memory source-destination pairs, see Fig. 3, and the pairs represent associated physical memory locations in the storage unit/physical memory which stores the instructions, see [0036]);
if the NEW-PAIR exists in the one or more memory tables, fetching the destination of the NEW-PAIR ([0045] and [0057]: if the pair exists in the LUT, the branch instruction is valid and is executed, which would involve fetching the instruction at the destination of the branch);
if the NEW-PAIR does not exist in the one or more memory tables, i) waiting until the speculation of the source of the NEW-PAIR has cleared as being non-speculative or one or more program counter clock cycles later, ii) updating the one or more memory tables, wherein the updating is associated with inclusion of the NEW-PAIR as a new authentic pair, and iii) fetching a non-speculative destination of the NEW-PAIR (this contingent limitation is not required under BRI of a method claim since it is contingent on the NEW-PAIR not existing in the tables, which the claim does not require; nonetheless, Lee [0045] and [0057] teaches that if the pair does not exist in the LUT, the branch is invalid and the execution unit does not execute the branch instruction, i.e., the source is nullified); and
if the speculation of the source of the NEW-PAIR does not clear as non-speculative, then the source of the NEW-PAIR is nullified (this contingent limitation is not required under BRI of a method claim since it is contingent on the speculation of the source of the NEW-PAIR not clearing as non-speculative, which the claim does not require; nonetheless, Lee [0045] and [0057] teaches that if the pair does not exist in the LUT, the branch is invalid and the execution unit does not execute the branch instruction, i.e., the source is nullified).
Lee does not teach:
receiving a new speculative source-destination pair (NEW-PAIR), wherein the source represents a speculative control-flow instruction identified by an associated source physical memory location where the speculative control-flow instruction is located and the destination represents an associated destination physical memory location where a next instruction to be executed is located, wherein the speculative control-flow instruction represents either a non-control-flow instruction mis-speculated as a control-flow instruction or an actual control-flow instruction;
the one or more memory tables each having memory source-destination pairs (OLD-PAIRS) associated with previous combinations of source-destination pairs that have successfully cleared as non-speculative source-destination pairs;
However, Solomatnikov teaches:
receiving a speculative control flow instruction, wherein the speculative control-flow instruction represents either a non-control-flow instruction mis-speculated as a control-flow instruction or an actual control-flow instruction ([0054]-[0055] describes that speculative execution may continue at step 530 or may be constrained at 540 based on the entry for the control flow instruction being activated, which indicates that the control flow instruction received for steps 510-520 is a speculative instruction);
checking if the speculative control flow instruction is associated with an activated entry (analogous to Lee checking if a pair is in the LUT), see [0053], the activated entry being associated a previously validated control flow instruction ([0057]: an entry is activated if the prediction is validated, see also [0019] describing that the entry may be activated after the first time the control flow instruction is executed or the first time a prediction based on the entry is validated);
Examiner notes that, while not required by the claim, Solomatnikov teaches: if the speculative control flow instruction is not associated with an activated entry (analogous to a branch not being in the LUT in Lee), i) waiting until the speculation of the source has cleared as being non-speculative or one or more program counter clock cycles later ([0056]: the control flow instruction may execute without speculation at step 542, that is, step 542 waits until speculation of the control flow instruction clears as being non-speculative), ii) updating the entry, wherein the updating is associated with inclusion of the PAIR as a new authentic pair ([0057]: step 548 activates the entry if the control flow instruction is validated), and iii) fetching the non-speculative destination ([0056]: continuing execution of the control flow instruction without speculative execution indicates that the instruction of the non-speculative destination of the control flow instruction will be fetched);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee to support speculative control flow instructions as taught by Solomatnikov such that the combination would check speculative control flow instructions against the LUT, which would include previous combinations of source and destination addresses that have been validated/cleared as non-speculative, and if the pair does not exist in the LUT, the combination would wait for the control flow instruction to be non-speculatively executed (i.e., clear as non-speculative), update the LUT to include the new PAIR, and fetch the non-speculative destination of the PAIR (when the pair is executed non-speculatively), and if the speculation does not clear as non-speculative, then the branch would be verified as invalid/nullified. One of ordinary skill in the art would have been motivated to make this modification to support speculative execution, which would enable the processor to achieve higher performance by avoiding pipeline delays, while preventing or mitigating side-channel attacks (Solomatnikov [0020] and [0054]).
Regarding claim 10, Lee in view of Solomatnikov teaches:
10. The method of claim 9, wherein the one or more memory tables includes a Speculative instruction Fetch Access Control Table (SFACT) housing authentic source- destination pairs (the LUT of the combination stores/houses validated/authentic source-destination pairs (as Solomatnikov teaches validating/authenticating the control flow instruction at step 545 of Fig. 5) and is a SFACT in the sense that it controls fetch access of speculative control flow instructions by ensuring that the speculative control flow instruction is verified before its target is fetched (otherwise the control flow instruction is invalidated/not executed, see Lee [0045])).
Regarding claim 10, Lee in view of Solomatnikov teaches:
11. The method of claim 9, wherein the speculation of the source of the NEW-PAIR is cleared as non-speculative when the source of the NEW-PAIR reaches the head of a Reorder Buffer (this contingent limitation is not required under BRI of a method claim since it is contingent on the source reaching the head of a Reorder Buffer, which the claim does not require).
Regarding claim 12, Lee in view of Solomatnikov teaches:
12. The method of claim 9, wherein the step of checking the NEW-PAIR against one or more memory tables includes using the source of the NEW-PAIR to look up the previous combinations of source-destination pairs that have successfully cleared as non- speculative source-destination pairs (OLD-PAIRs) (Lee [0059] teaches checking if the combination of the branch instruction address and the branch target address are in the LUT, which indicates that both the branch instruction address (i.e., the source) and the branch target address are used to look up the LUT for previous combinations of pairs that successfully cleared as non-speculative (in the combination)).
Regarding claim 13, Lee in view of Solomatnikov teaches:
13. The method of claim 9, wherein the step of checking the NEW-PAIR against one or more memory tables includes using the destination of the NEW-PAIR to look up the previous combinations of source-destination pairs that have successfully cleared as non- speculative source-destination pairs (OLD-PAIRs) (Lee [0059] teaches checking if the combination of the branch instruction address and the branch target address are in the LUT, which indicates that both the branch instruction address and the branch target address (i.e., the destination) are used to look up the LUT for previous combinations of pairs that successfully cleared as non-speculative (in the combination)).
Regarding claim 15, Lee in view of Solomatnikov teaches:
15. The method of claim 9, wherein each of the one or more memory tables associated with the previous combinations of source-destination pairs that have successfully cleared as non-speculative source-destination pairs (OLD-PAIRS) are amended via hardware or software control (the combination updates/amends entries in the LUT with pairs that have cleared as non-speculative (see Solomatnikov Fig. 5 teaching activating/updating an entry at step 548 once the prediction is validated at step 545), which is done via hardware or software control since any step in a processor occurs under hardware or software control).
Regarding claim 16, Lee in view of Solomatnikov teaches:
16. The method of claim 9, wherein the source of the NEW-PAIR or the OLD-PAIRs is i) a complete instruction or ii) a micro-operation included in a complex instruction comprising a plurality of micro- operations (Lee [0057]: the source is a branch instruction, which is a complete instruction).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2008/0256346 in view of Solomatnikov US 2019/0286443, and Favor US 2022/0107784.
Regarding claim 17, Lee in view of Solomatnikov teaches:
17. The method of claim 9,
Lee in view of Solomatnikov does not teach:
wherein the associated source physical memory location and the associated destination physical memory location are presented as partial addresses and the step of checking the NEW-PAIR against one or more memory tables includes finding a best match.
However, Favor teaches using a tag/partial address to access a memory, see [0070].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Lee in view of Solomatnikov to access the LUT using partial source and destination addresses/tags as taught by Favor such that the combination would select/find an entry with matching tags, i.e., a best match. One of ordinary skill in the art would have been motivated to make this modification to reduce the number of bits required for accessing entries in the LUT, which would reduce hardware requirements.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee US 2008/0256346 in view of Solomatnikov US 2019/0286443, and Zhang US 2008/0263315.
Regarding claim 14, Lee in view of Solomatnikov teaches:
14. The method of claim 9,
Lee in view of Solomatnikov does not teach:
wherein one or more virtual memory locations associated with each of the source and the destination of the NEW-PAIR or the OLD-PAIRs are represented as a coarse-grained set of locations augmented with a bit mask to identify one or more finer-grain locations contained within the coarse-grained set.
However, Zhang teaches a segment/mask addressing mode which divides memory locations into segments and identifies locations in a segment using a mask, see [0022]-[0026]. Examiner notes that while the description may be directed to register addressing, the teaching apply more broadly to memory addressing.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the LUT of Lee in view of Solomatnikov and Hennessy to use the segment/mask address taught by Zhang such that the combination would represent the source and destinations as segments (i.e., a course-grained set of locations) augmented with a mask (i.e., a bit mask to identify finer-grain locations). One of ordinary skill in the art would have been motivated to make this modification to improve addressing efficiency (Zhang [0022] and [0027]).
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
