Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This Office Action is responsive to the communication filed 5/24/2024.
Information Disclosure Statement
2. The information disclosure statements submitted on 12/9/2025 and 12/12/2025 were filed after the mailing date of the instant application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections – 35 USC 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
4. Claim 1 is rejected under 35 USC 101 as being directed to an abstract idea without being integrated into a practical application or being significantly more.
Regarding claim 1, the claim recites the limitations “defining a bank as a specified row exclusive or-ed with a specific column;” “when addressing a row, mapping a bank I to an index I xor the row;” and “when addressing a column, mapping a bank I to an index i xor the row;” Broadly interpreted, the aforementioned steps are directed to mental processes as said steps could be performed in the human mind. Therefore, the claims recite an abstract idea.
Said abstract idea and/or judicial exception is not integrated into a practical application as the claim does not recite any other active steps that could be considered that the abstract idea is being integrated into a practical application. It’s noted that the claim recites the operations “storing data in a single-port memory;” However, said operation is not sufficient to consider that the abstract idea is being interpreted into a practical application. Said operation is recited at a high level of generality in gathering/processing/storing information, which is a form of insignificant extra-solution activity.
It’s also noted that the claims recite additional limitation/elements (i.e., memory, etc.,). However, said additional elements are recited at a high-level of generality (i.e., as a generic computing device performing a generic computer functions) such that it amounts no more than mere instructions to apply the exception or abstract idea using generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements/limitations/embodiments that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. As mentioned above, although the claims recite additional elements, said elements taken individually or as a combination, do not result in the claim amounting to significantly more than the abstract idea because as the additional elements perform generic computer content distributing functions routinely used in information technology field. As discussed above, the additional elements recited at a high-level of generality such that they amount no more than mere instructions to apply the exception using a generic computer component. Therefore, the claim is directed to non-statutory subject matter.
Claim Rejections – 35 USC 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
6. Claims 1-8 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 1, claim 1 recites the limitation “specified row exclusive or-ed with a specific column.” It’s unclear how to perform an XOR operation for a specific row with a specific column. The specification does not provide any explanation how the claimed XOR operation is performed. It’s unclear whether value stored in a position ith of the specific row is XOR’ed with a value stored in a position ith of the specific column; and it’s unclear how to perform the operation when the size of the row is different than the size of column. Therefore, the claim is found indefinite.
Regarding claim 1, claim 1 recites the limitation “mapping a bank I to an index i xor the row.” It’s unclear how to perform XOR operation for an index (i.e., a single value) to the row (i.e., a plurality of value stored in the row). In addition, it’s unclear whether to perform mapping the bank i to index i, then perform the XOR operation, or mapping a bank i to the index i, then performing the XOR operation.
Claim 4 recites the limitation "a chunk of data is received from the columns" in line 3. There is insufficient antecedent basis for this limitation in the claim. A minor amendment to disclose multiple, several, a plurality, etc. of columns prior to the recitation of “the columns” would overcome this portion of the rejection.
Claim 5 recites the limitation "a chunk of data is received from the rows" in line 3. There is insufficient antecedent basis for this limitation in the claim. A minor amendment to disclose multiple, several, a plurality, etc. of rows prior to the recitation of “the columns” would overcome this portion of the rejection.
Claim 6 recites the limitation "wherein the number of conditional step nodes" in line 2. There is insufficient antecedent basis for this limitation in the claim, although the term “a network of conditional step nodes” is previously recited in the claim. Amending the claim language to “a number of step nodes” would overcome this portion of the rejection.
Claim 7 recites the limitation "where the conditional swap nodes…" in line 3. There is insufficient antecedent basis for this limitation in the claim, although the term “a network of conditional step nodes” is previously recited in the claim. It is unclear if the applicant intended to reference of the previously claimed “network of conditional step nodes” or introduce a plurality of “conditional swap nodes”.
Regarding claim 7, it is also unclear if the claimed “a network of conditional step nodes” refers to or claims dependency upon the “network of conditional step nodes” previously disclosed in claim 6.
Claims 2-3, and 8 depend upon claim 1 and, thus, are also rejected under 35 USC 112(b).
Claim Rejections – 35 USC 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-5 are rejected under 35 USC 103 as being unpatentable over Khedr et al (US 2018/0294950) in view of Howard (US 2017/0346622).
Regarding claim 1, Khedr et al teaches a method for conflict-free memory accesses (par [0063], lines 7-8, which discloses providing storage unit access for homomorphic processing function), the method comprising:
storing data in a single-port memory (par [0020], “single-stage unit”), wherein:
the memory can be accessed by row or column (par [0064], “row-by-row…column-by-column”).
Khedr et al does not explicitly teach wherein the data is arranged in a scrambled ordering; defining a bank as a specified row exclusive or-ed with a specific column; when addressing a row, mapping a bank i to an index i xor the row; and when addressing a column, mapping a bank i to an index i xor the row.
However, Howard teaches the data is arranged in a scrambled ordering (par [0061], lines 5-10, “order of buffer data bits is scrambled”);
defining a bank as a specified row exclusive or-ed with a specific column (par [0098], lines 1-8, which discloses scrambling row and column keys being XOR-ed with the rows and columns);
when addressing a row, mapping a bank i to an index i xor the row (par [0101], lines 16-22, which discloses XOR-ing a row to form a row ciphertext); and
when addressing a column, mapping a bank i to an index i xor the row (par [0101], lines 16-22, which discloses XOR-ing a row to form a row ciphertext).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Howard within the disclosure of Khedr et al in order to provide the predictive result of improving secure storage in a homomorphic encryption system by applying multidimensional encryption (as disclosed in fig. 13 & par [0042] of Howard) because this feature would provide Khedr et al with additional block ciphering of each storage row and column using row keys and column keys appended to each storage block (as disclosed in par [0071-0072] of Howard).
Regarding claim 2, Khedr et al and X et al teach the limitations of claim 1.
Khedr et al further teaches using permutation processing elements to reorder the data from the memory (par [0118], lines 6-7, “rearranging the elements in a different order”).
Regarding claim 3, Khedr et al and X et al teach the limitations of claim 1.
Khedr et al further teaches wherein the memory is accessed via a single-cycle operation per chunk (par [0110], lines 9-10, “operation carried out in a single clock cycle”), wherein a chunk is defined as a number of coefficients to be accessed per cycle (par [0027], “’n’ represents a degree of a polynomial associated with the coefficient values”).
Regarding claim 4, Khedr et al and X et al teach the limitations of claim 1.
Khedr et al further teaches wherein using permutation processing elements to reorder the data from the memory comprises:
when addressing a row, a chunk of data is received from the columns (par [0118], lines 6-12, “rearranging the elements in a different order…until all column elements are read”).
Regarding claim 5, Khedr et al and X et al teach the limitations of claim 1.
Khedr et al further teaches wherein using permutation processing elements to reorder the data from the memory comprises:
when addressing a column, a chunk of data is received from the rows (par [0118], lines 1-7, “elements along the row of the Ctxt are read first”).
9. Claims 6-8 are rejected under 35 USC 103 as being unpatentable over Khedr et al (US 2018/0294950) in view of Howard (US 2017/0346622), further in view of Fei et al (US 2022/0368514).
Regarding claim 6, Khedr et al and Howard do not explicitly teach wherein the permutation processing elements includes a network of conditional step nodes, wherein the number of conditional step nodes is related to a size of the permutation processing element.
However, Fei et al teaches wherein the permutation processing elements includes a network of conditional step nodes (par [0083], lines 10-13, “equal sized groups, and permutations take place within each group”), wherein the number of conditional step nodes is related to a size of the permutation processing element (par [0082], “permutation as limb, with its size equal to that of a cache bank”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Fei et al with the teachings of Khedr et al and Howard in order to provide the predictive result of increasing security in a cryptographic environment by improving functionality when protecting against potential attacks when implementing grouping memory bank access requests into distinct memory-related transactions (as disclosed in par [0043] of Fei et al) because this feature collects previously determined coalescing attack and leaked memory access patterns for ensuring future attempts containing data that match previous malicious patterns are blocked.
Regarding claim 7, Khedr et al and Howard do not explicitly teach wherein the permutation processing elements includes a network of conditional step nodes, where the conditional swap nodes either swap inputs or keep the inputs the same based on a control value.
However, Fei et al teaches wherein the permutation processing elements includes a network of conditional step nodes (par [0083], lines 10-13, “equal sized groups, and permutations take place within each group”), where the conditional swap nodes either swap inputs or keep the inputs the same based on a control value (par [0066], “first data and second data are swapped”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Fei et al with the teachings of Khedr et al and Howard according to the motivation disclosed regarding claim 6.
Regarding claim 8, Khedr et al and Howard do not explicitly teach wherein an address bit determines whether the memory is to be accessed to address a row or column.
However, Fei et al teaches wherein an address bit determines whether the memory is to be accessed to address a row or column (par [0041], lines 8-10, “field of a memory is used to locate the cache set (row)”).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Fei et al with the teachings of Khedr et al and Howard according to the motivation disclosed regarding claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Randy A. Scott whose telephone number is (571) 272-3797. The examiner can normally be reached on Monday-Thursday 7:30 am-5:00 pm, second Fridays 7:30 am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Luu Pham can be reached on (571) 270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RANDY A SCOTT/Primary Examiner, Art Unit 2439 20251219