Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
The instant application having Application No. 18/674,901 has claims 1-7 and 9-13 pending filed on 05/26/2024; there are 2 independent claim and 10 dependent claims, all of which are ready for examination by the examiner. The applicant canceled the dependent claim 8 (dated 09/10/2025).
Response to Arguments
This Office Action is in response to applicant’s communication filed on September 10, 2025 in response to PTO Office Action dated June 12, 2025. The Applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
Objections to the Claims
In view of the applicant’s amendment to the dependent claim 2 (dated 09/10/2025), the objection to the claim 2 is withdrawn.
Claim Rejections
Claim Rejections - 35 USC § 101
In view of the applicant’s amendments to the independent claims 1 and 11 (dated 09/10/2025), the claim rejection under 35 U.S.C. § 101 for judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more of the claims 1-7 and 9-13 is withdrawn.
Claim Rejections - 35 USC § 103
35 USC § 103 Rejection of claims 1-7 and 9-13
Applicant's arguments filed on 09/10/2025 with respect to the claims 1-7 and 9-13 have been fully considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al (US PGPUB 20220404965) in view of Lin et al (US PGPUB 20190220392) and in further view of Osterlund et al (US PGPUB 20220138098).
As per claim 1:
Sasaki teaches:
“A method for performing garbage collection (GC) management of a memory device with aid of dedicated information control, the method being applied to a memory controller of the memory device” (Paragraph [0023], Paragraph [0031] and Paragraph [0057] (a processing procedure (method) of the memory system where the memory system includes a non-volatile memory & a controller and the garbage collection control unit executes garbage collection (GC) for the non-volatile memory))
“the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising a plurality of NV memory elements, each NV memory element of the plurality of NV memory elements comprising a plurality of blocks, the method comprising” (Paragraph [0031] (The memory system includes a non-volatile memory and a controller where the non-volatile memory includes a plurality of blocks))
“utilizing the memory controller to receive at least one first command from a host device through a transmission interface circuit within the memory controller” (Paragraph [0031] (a memory system is capable of being connected to a host and the controller controls write/read of data to/from the non-volatile memory in response to a command from the host))
“and perform at least one accessing operation on the NV memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device” (Paragraph [0031] (The controller selects a write destination block based on a size of write data requested to be written to the non-volatile memory by a write command from the host))
“and utilizing the memory controller to execute a GC procedure to start performing GC on the NV memory, wherein the GC procedure comprises” (Paragraph [0057] and Fig. 1 (the garbage collection control unit executes garbage collection (GC) (which is component of the controller 5) for the non-volatile memory which includes))
“dividing a memory region of a volatile memory within the memory controller into multiple sub-regions according to the plurality of NV memory elements” (Paragraph [0041], Paragraph [0045], Paragraph [0046] and Paragraph [0048] (the non-volatile memory may be configured to divide the memory regions into sub-regions for storing the data, the a look up table (LUT) and the a valid data map (VDM) table corresponding to the volatile memory in the controller consisting of the memory sub-regions of write and read data buffers and memory cache consisting the sub-regions for LUT and VDM )
Sasaki does not EXPLICITLY teach: selecting multiple source blocks from the plurality of blocks comprising at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements; reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks; reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks; comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data; and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element; wherein the first GC operation and the second GC operation are are performed in parallel processing.
However, in an analogous art, Lin teaches:
“selecting multiple source blocks from the plurality of blocks comprising” (Paragraph [0008] (the source information indicates a source location of the valid data, the source location is located in one or more source blocks))
“at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements” (Paragraph [0032] (the memory controller may check whether the page PAGE(x) is valid which the memory controller may determine when the spare region of the page PAGE(x) is not blank, and no uncorrectable ECC (UECC) error of the spare region occurs, otherwise, the memory controller 110 may determine the page PAGE(x) as an empty page, which means the page PAGE(x) is not valid))
“reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks” (Paragraph [0028] (the memory controller may store or manage (e.g. change and/or update) at least one physical-to-logical (P2L) address mapping table in the volatile memory, such as one or more P2L address mapping tables))
“reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks” (Paragraph [0028] (the memory controller may update the global logical-to-physical (L2P) address mapping table, directly, according to the temporary physical-to-logical (P2L) address mapping table))
“comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data” (Paragraph [0028] (the memory controller may record the respective source information of the aforementioned valid data such as the respective source locations of the aforementioned valid data in the temporary P2L address mapping table to generate the multiple sets of P2L mapping information and the memory controller may update the global L2P address mapping table directly, according to the temporary P2L address mapping table))
“the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element” (Paragraph [0026] (when performing a GC operation, the memory controller operating based on the method may store valid data collected from one or more source blocks GCs into respective data regions PDR of multiple pages of one or more destination blocks GCd, and may write respective source information of the aforementioned valid data, such as respective source locations of the aforementioned valid data, into respective spare regions PSR of the multiple pages, where a plurality of blocks within aforementioned at least one NV memory element may comprise the one or more source blocks GCs and the one or more destination blocks GCd)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Lin and apply them on teachings of Sasaki for the method “selecting multiple source blocks from the plurality of blocks comprising at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements; reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks; reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks; comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data; the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element”. One would be motivated as the memory controller may selectively perform a small portion of tasks that has previously completed in the GC operation again, to guarantee correctness of the data and/or the reliability of data storage, can quickly perform recovery regarding the GC mechanism, without greatly increasing the overall cost and can improve performance of memory devices without introducing side effects (Lin, Paragraph [0027]).
Sasaki and Lin do not EXPLICITLY teach: and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; wherein the first GC operations and the second GC operations are performed in parallel processing.
However, in an analogous art, Osterlund teaches:
“and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions” (Paragraph [0103] and Paragraph [0105] (a GC thread is configured to perform garbage collection, it iteratively performs GC cycles based on a schedule and/or an event trigger where a GC cycle includes a set of (multiple) GC operations for reclaiming memory locations and a heap is separated into different regions where a first region stores objects that have not yet satisfied a criteria for being promoted from the first region to a second region and a second region stores objects that have satisfied the criteria for being promoted from the first region to the second region))
“wherein the first GC operations and the second GC operations are performed in parallel processing” (Paragraph [0104] (multiple GC threads may perform GC operations in parallel and the multiple GC threads working in parallel may be referred to as a “parallel collector”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Osterlund and apply them on teachings of Sasaki and Lin for the method “and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; wherein the first GC operations and the second GC operations are performed in parallel processing”. One would be motivated as various different GC processes for performing garbage collection achieve different memory efficiencies, time efficiencies, and/or resource efficiencies (Osterlund, Paragraph [0107]).
As per claim 2:
Sasaki, Lin and Osterlund teach the method of claim 1 above.
Sasaki further teaches:
“wherein the at least one NV memory element comprises a plurality of NV memory elements a plurality of NV memory elements, and the multiple sub-regions represent multiple NV-memory-element-dedicated memory regions respectively corresponding to the plurality of NV memory elements” (Paragraph [0037] and Paragraph [0041] (the memory cell array of the non-volatile memory includes a plurality of blocks, and each of the blocks is organized by a large number of pages, each page is a unit of a data writing operation and a data reading operation and the non-volatile memory may be configured to divide the memory (region) for storing the data)).
As per claim 3:
Sasaki, Lin and Osterlund teach the method of claim 2 above.
Sasaki further teaches:
“wherein the plurality of NV memory elements represent a plurality of flash memory dies, and the multiple sub-regions represent multiple die-dedicated memory regions respectively corresponding to the plurality of flash memory dies” (Paragraph [0036] and Paragraph [0075] (the non-volatile memory including NAND type flash memory includes a plurality of memory cells (memory cell array) arranged in a matrix and the namespace is a region obtained by logically dividing a memory region (plurality of blocks) included in the non-volatile memory (flash memory))).
As per claim 4:
Sasaki, Lin and Osterlund teach the method of claim 2 above.
Sasaki further teaches:
“wherein the plurality of NV memory elements represent a plurality of flash memory chips, and the multiple sub- regions represent multiple chip-dedicated memory regions respectively corresponding to the plurality of flash memory chips” (Paragraph [0036] and Paragraph [0051] (the non-volatile memory including NAND type flash memory includes a plurality of memory cells (memory cell array) arranged in a matrix and the controller functions as a flash translation layer (FTL) configured to perform data management and block management of the non-volatile memory or the NAND type flash memory)).
As per claim 5:
Sasaki, Lin and Osterlund teach the method of claim 1 above.
However, in an analogous art, Lin teaches:
“wherein the memory controller is arranged to write host data from the host device into at least one block among the plurality of blocks, and correspondingly update a global L2P address mapping table in the NV memory, for indicating mapping relationships from logical addresses to physical addresses, wherein the global L2P address mapping table is divided into a plurality of local L2P address mapping tables” (Paragraph [0024] and Paragraph [0033] (the memory controller may write the source information into a P2L address mapping table to build or rebuild the P2L address mapping table, the memory controller may store a global logical-to-physical (L2P) address mapping table in the NV memory, maintain (e.g. change and/or update) the global L2P address mapping table, the global L2P address mapping table may comprise multiple local L2P address mapping tables, which may be referred to as L2P address mapping tables))
“and the at least one latest L2P address mapping table represents at least one local L2P address mapping table corresponding to the multiple source blocks among the plurality of local L2P address mapping tables” (Paragraph [0024] (the memory controller may store at least one L2P address mapping table (e.g. one or more L2P address mapping tables) of the L2P address mapping tables into the volatile memory as a temporary L2P address mapping table, and may maintain (e.g. change and/or update) the temporary L2P address mapping table)).
As per claim 6:
Sasaki, Lin and Osterlund teach the method of claim 1 above.
Lin further teaches:
“comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store said valid-data location information in the multiple sub-regions, respectively further comprises” (Paragraph [0028] (the memory controller may record the respective source information of the aforementioned valid data such as the respective source locations of the aforementioned valid data in the temporary P2L address mapping table to generate the multiple sets of P2L mapping information and the memory controller may update the global L2P address mapping table directly, according to the temporary P2L address mapping table includes))
“indicating locations of respective valid data of the plurality of NV memory elements, respectively” (Paragraph [0028] (the memory controller may record the respective source locations of the valid data in the temporary P2L address mapping table to generate the multiple sets of P2L mapping information)).
As per claim 7:
Sasaki, Lin and Osterlund teach the method of claim 6 above.
Sasaki further teaches:
“wherein said valid-data location information respectively stored in the multiple sub- regions comprises multiple sets of valid-data location information corresponding to the plurality of NV memory elements” (Paragraph [0041] (the non-volatile memory may be configured to divide the memory into regions for storing the data, the a look up table (LUT) and the a valid data map (VDM)))
“and the memory controller is arranged to select a dedicated memory region corresponding to any NV memory element of the plurality of NV memory elements from the multiple sub-regions, and generate and store a set of valid-data location information corresponding to the any NV memory element among the multiple sets of valid-data location information in the dedicated memory region, for indicating locations of valid data of all source blocks belonging to the any NV memory element among the multiple source blocks” (Paragraph [0040] and Paragraph [0041]( (the non-volatile memory may be configured to divide the memory into regions for storing the data, the a look up table (LUT) and the a valid data map (VDM) and the non-volatile memory further stores a valid data map (VDM) where the VDM corresponds to the data for managing the validity of the data written to the physical address in the non-volatile memory)).
As per claim 9:
Sasaki, Lin and Osterlund teach the method of claim 1 above.
Sasaki further teaches:
“wherein in the first GC operation, the memory controller reads first valid data of the first NV memory element according to a first set of valid-data location information stored in a first dedicated memory region, and writes the first valid data into the first target block being a first destination block belonging to the first NV memory element” (Paragraph [0344] and Paragraph [0345] (the write destination blocks are switched based on the size of the write data of the host, and in the garbage collection (GC), with respect to a block which transits from the first block which is one of the being-written blocks to the written block, reference of the flag information (bit scan) becomes unnecessary when the valid data in the block is moved))
“and in the second GC operation, the memory controller reads second valid data of the second NV memory element according to a second set of valid-data location information stored in a second dedicated memory region, and writes the second valid data into the second target block being a second destination block belonging to the second NV memory element” (Paragraph [0345] and Paragraph [0346] (the block which transits from the third block to the written block does not require reference of the management data and in the garbage collection (GC), if the block which transits to the written block from the first block or the third block is selected as a target, an effect of overhead reduction will be expected)).
As per claim 10:
Sasaki, Lin and Osterlund teach the method of claim 1 above.
Lin further teaches:
“wherein said valid-data location information respectively stored in the multiple sub-regions comprises multiple sets of valid-data location information corresponding to the plurality of NV memory elements” (Paragraph [0026] (the memory controller may store valid data collected from one or more source blocks GCs into respective data regions PDR of multiple pages of one or more destination blocks GCd, and may write respective source information of the aforementioned valid data, such as respective source locations of the valid data, into respective spare regions PSR of the multiple pages, where a plurality of blocks within at least one NV memory element))
“wherein the multiple sets of valid-data location information comprise a first set of valid-data location information corresponding to the first NV memory element and a second set of valid-data location information corresponding to the second NV memory element” (Paragraph [0025] and Paragraph [0028] (the memory controller may record the respective source information of the aforementioned valid data such as the respective source locations of the aforementioned valid data in the temporary P2L address mapping table to generate the multiple sets of P2L mapping information, a first set of the multiple sets of mapping information is arranged for mapping a first logical address to a first physical address, and a second set of the multiple sets of mapping information is arranged for mapping a second logical address to a second physical address)).
“and the first set of valid-data location information and the second set of valid-data location information are stored in a first dedicated memory region and a second dedicated memory region among the multiple sub-regions, respectively” (Paragraph [0026] (the memory controller may store valid data collected from one or more source blocks GCs into respective data regions (dedicated memory region among the multiple sub-regions) PDR of multiple pages of one or more destination blocks GCd, and may write respective source information of the aforementioned valid data, such as respective source locations of the aforementioned valid data, into respective spare regions PSR of the multiple pages, of the plurality of NV memory elements)).
As per claim 11:
Sasaki teaches:
“A memory controller of the memory device” (Paragraph [0042] (the controller includes a non-volatile memory controller and memory))
“the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising a plurality of NV memory elements, each NV memory element of the plurality of NV memory elements comprising a plurality of blocks, the method comprising” (Paragraph [0031] (the memory system includes a non-volatile memory and a controller where the non-volatile memory includes a plurality of blocks))
“a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device” (Paragraph [0031] (the controller controls write/read of data to/from the non-volatile memory in response to a command from the host))
“to allow the host device to access the NV memory through the memory controller” (Paragraph [0031] (a memory system is capable of being connected to a host and the controller controls write/read of data to/from the non-volatile memory in response to a command from the host))
“wherein the processing circuit is arranged to perform garbage collection (GC) management of the memory device with aid of dedicated information control” (Paragraph [0053] (by executing the control program, the processor realizes functional units such as a garbage collection control unit))
“and a transmission interface circuit, arranged to perform communications with the host device” (Paragraph [0043] (the communication interface control unit controls communication between the host and the memory system, specifically, the communication interface control unit receives various commands from the host))
“wherein: the memory controller receives at least one first command from the host device through the transmission interface circuit within the memory controller” (Paragraph [0031] (a memory system is capable of being connected to a host and the controller controls write/read of data to/from the non-volatile memory in response to a command from the host))
“and performs at least one accessing operation on the NV memory according to the at least one first command, wherein the at least one first command indicates at least one write request from the host device” (Paragraph [0031] (the controller selects a write destination block based on a size of write data requested to be written to the non-volatile memory by a write command from the host))
“and the memory controller executes a GC procedure to start performing GC on the NV memory, wherein the GC procedure comprises” (Paragraph [0057] and Fig. 1 (the garbage collection control unit executes garbage collection (GC) (which is component of the controller 5) for the non-volatile memory which includes))
“dividing a memory region of a volatile memory within the memory controller into multiple sub-regions according to the plurality of NV memory elements” (Paragraph [0041], Paragraph [0045], Paragraph [0046] and Paragraph [0048] ( the non-volatile memory may be configured to divide the memory regions into sub-regions for storing the data, the a look up table (LUT) and the a valid data map (VDM) table corresponding to the volatile memory in the controller consisting of the memory sub-regions of write and read data buffers and memory cache consisting the sub-regions for LUT and VDM)).
Sasaki does not EXPLICITLY teach: selecting multiple source blocks from the plurality of blocks comprising; at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements; reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks; reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks; comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data; and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element; wherein the first GC operation and the second GC operation are are performed in parallel processing.
However, in an analogous art, Lin teaches:
“selecting multiple source blocks from the plurality of blocks comprising” (Paragraph [0008] (the source information indicates a source location of the valid data, the source location is located in one or more source blocks))
“at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements” (Paragraph [0032] (the memory controller may check whether the page PAGE(x) is valid which the memory controller may determine when the spare region of the page PAGE(x) is not blank, and no uncorrectable ECC (UECC) error of the spare region occurs, otherwise, the memory controller 110 may determine the page PAGE(x) as an empty page, which means the page PAGE(x) is not valid))
“reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks” (Paragraph [0028] (the memory controller may store or manage (e.g. change and/or update) at least one physical-to-logical (P2L) address mapping table in the volatile memory, such as one or more P2L address mapping tables))
“reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks” (Paragraph [0028] (the memory controller may update the global logical-to-physical (L2P) address mapping table, directly, according to the temporary physical-to-logical (P2L) address mapping table))
“comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data” (Paragraph [0028] (the memory controller may record the respective source information of the aforementioned valid data such as the respective source locations of the aforementioned valid data in the temporary P2L address mapping table to generate the multiple sets of P2L mapping information and the memory controller may update the global L2P address mapping table directly, according to the temporary P2L address mapping table))
“the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element” (Paragraph [0026] (when performing a GC operation, the memory controller operating based on the method may store valid data collected from one or more source blocks GCs into respective data regions PDR of multiple pages of one or more destination blocks GCd, and may write respective source information of the aforementioned valid data, such as respective source locations of the aforementioned valid data, into respective spare regions PSR of the multiple pages, where a plurality of blocks within aforementioned at least one NV memory element may comprise the one or more source blocks GCs and the one or more destination blocks GCd)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Lin and apply them on teachings of Sasaki for the method “selecting multiple source blocks from the plurality of blocks comprising at least a first source block from a first sub-region of the multiple sub-regions corresponding to a first NV memory element of the plurality of NV memory elements, and at least a second source block from a second sub-region of the multiple sub-regions corresponding to a second NV memory element of the plurality of NV memory elements; reading respective physical-to-logical (P2L) address mapping tables of the multiple source blocks; reading at least one latest logical-to-physical (L2P) address mapping table within the NV memory according to the respective P2L address mapping tables of the multiple source blocks; comparing the respective P2L address mapping tables of the multiple source blocks and the at least one latest L2P address mapping table to generate and store valid-data location information in the multiple dedicated memory regions, respectively, for indicating locations of per-NV-memory-element valid data; the multiple GC operations comprising at least a first GC operation and a second GC operation respectively corresponding to the first NV memory element and the second NV memory element, wherein the first GC operation is performed according to a first target block from the first sub-region corresponding to the first NV memory element, and the second GC operation is performed according to a second target block from the second sub-region corresponding to the second NV memory element”. One would be motivated as the memory controller may selectively perform a small portion of tasks that has previously completed in the GC operation again, to guarantee correctness of the data and/or the reliability of data storage, can quickly perform recovery regarding the GC mechanism, without greatly increasing the overall cost and can improve performance of memory devices without introducing side effects (Lin, Paragraph [0027]).
Sasaki and Lin do not EXPLICITLY teach: and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; wherein the first GC operations and the second GC operations are performed in parallel processing.
However, in an analogous art, Osterlund teaches:
“and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions” (Paragraph [0103] and Paragraph [0105] (a GC thread is configured to perform garbage collection, it iteratively performs GC cycles based on a schedule and/or an event trigger where a GC cycle includes a set of (multiple) GC operations for reclaiming memory locations and a heap is separated into different regions where a first region stores objects that have not yet satisfied a criteria for being promoted from the first region to a second region and a second region stores objects that have satisfied the criteria for being promoted from the first region to the second region))
“wherein the first GC operations and the second GC operations are performed in parallel processing” (Paragraph [0104] (multiple GC threads may perform GC operations in parallel and the multiple GC threads working in parallel may be referred to as a “parallel collector”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Osterlund and apply them on teachings of Sasaki and Lin for the method “and performing multiple GC operations according to said valid-data location information respectively stored in the multiple dedicated memory regions; wherein the first GC operations and the second GC operations are performed in parallel processing”. One would be motivated as various different GC processes for performing garbage collection achieve different memory efficiencies, time efficiencies, and/or resource efficiencies (Osterlund, Paragraph [0107]).
As per claim 12:
Sasaki, Lin and Osterlund teach the memory device comprising the memory controller of claim 11 above.
Sasaki further teaches:
“wherein the memory device comprises: the NV memory, configured to store information” (Paragraph [0033] (the memory system is a semiconductor storage device configured to write data (store data) to a non-volatile memory)).
“and the memory controller, coupled to the NV memory, configured to control operations of the memory device” (Paragraph [0031] (the memory system includes a non-volatile memory and a controller where the controller controls write/read of data to/from the non-volatile memory in response to a command from the host)).
As per claim 13:
Sasaki, Lin and Osterlund teach the memory device claim 12 above.
Sasaki further teaches:
“the host device, coupled to the memory device, wherein the host device comprises” (Paragraph [0031] (a memory system is capable of being connected to a host which includes)).
“at least one processor, arranged for controlling operations of the host device” (Paragraph [0034] (the host is an information processing device that operates as a host device for the memory system and can be realized as a personal computer)).
“wherein the memory device provides the host device with storage space” (Paragraph [0031] (the memory system includes a non-volatile memory and a controller where the controller controls write/read of data to/from the non-volatile memory in response to a command from the host)).
Also, Lin further teaches:
.“and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device” (Paragraph [0010] (the host device may comprise: at least one processor, arranged for controlling operations of the host device; and a power supply circuit, coupled to the at least one processor, arranged for supplying power to the at least one processor and the memory device)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi Hyoung Pil, (US PGPUB 20220413738), a memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.
Byun Eu-Joon, (US PGPUB 20200387447), a memory system may include a memory device including a plurality of dies each including a plurality of memory blocks; and a controller including a memory and a garbage collection module configured to perform a garbage collection operation by transmitting data to the memory device through at least one of a plurality of data paths, wherein the garbage collection module: determines whether the garbage collection operation is executable in parallel with a host task operation, depending on which of the plurality of dies includes a target block of the garbage collection operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/Kamal K Dewan/
Examiner, Art Unit 2163
/TONY MAHMOUDI/Supervisory Patent Examiner, Art Unit 2163