Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This office action is in response to the application filed on 05/27/2024.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawing
The drawings filed on 05/27/2024 are acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/30/2024 is in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has been considered by the examiner.
Claims 1-22 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Joukou et al. (US 2006/0193091 A1), hereinafter Joukou’ in view of Hu (US 2005/0168511 A1).
In re to claim 1, Joukou disclose a circuit apparatus comprising a power conversion circuit (i.e. fig. 1, see par. [0039]), and a control circuit (i.e. 1 and 10, see pars. [0039, 0043, 0086]), which controls the power conversion circuit (i.e. see par. [0039, 0043, 0086], wherein the power conversion circuit includes: a control terminal to which a control signal from the control circuit is input (i.e. the control input from the controllers 1 and 10 to the power converter circuit 20, see par. [0043]); an output terminal from which an output signal is output to the control circuit (i.e. the detections signal from 32 to and the feedback signal from the sensor 23 to the controller circuit 10, see pars. [0040 and 0044-0045]). Except, Joukou fail to explicitly disclose that a data identification unit which identifies an input data signal input to the output terminal. Whereas Hu teaches that a data identification unit (i.e. 202, 204, 206, 208 and 210. fig. 2B, see pars. [0007]) which identifies an input data signal input to the output terminal (i.e. the signal transmission line 112, fig. 2B, see the Abstract and par. [0043]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit apparatus of Joukou by incorporating the data identification unit of Hu to help identify the different types of signals transmitted on the same transmission circuit between the controller and the power conversion circuits.
In re to claim 4, Joukou disclose the circuit apparatus circuit (i.e. fig. 1, see par. [0039]) according to claim 1, wherein the output signal includes an alarm signal (i.e. a protection alarm signal FO (Fault Out), see par. [0044] indicating whether the power conversion circuit is put into a preset state (i.e. see pars. [0044-0046]).
In re to claim 5, Joukou disclose the circuit apparatus circuit (i.e. fig. 1, see par. [0039]) according to claim 1, wherein the output signal includes an output data signal output by the power conversion circuit (i.e. power source circuit 11 extracts electric energy from the driving control signal CS transmitted from the interface circuit 2, and supplies a power source voltage to respective circuits provided within the IPM 3. In addition, the driving control signal CS transmitted from the interface circuit 2 is outputted to a driver circuit 22 via the AND gate 12, the photocoupler 31, and an AND gate 21, see fig. 1 and par. [0044]).
In re to claim 16, Joukou disclose a power conversion circuit (i.e. fig. 1, see par. [0039]) which is controlled by a control circuit (i.e. 1 and 10, the power conversion circuit comprising: a control circuit (i.e. 1 and 10, see pars. [0039, 0043, 0086]), which controls the power conversion circuit (i.e. see par. [0039, 0043, 0086], wherein the power conversion circuit includes: a control terminal to which a control signal from the control circuit is input (i.e. the control input from the controllers 1 and 10 to the power converter circuit 20, see par. [0043]); an output terminal from which an output signal is output to the control circuit (i.e. the detections signal from 32 to and the feedback signal from the sensor 23 to the controller circuit 10, see pars. [0040 and 0044-0045]). Except, Joukou fail to explicitly disclose that a data identification unit which identifies an input data signal input to the output terminal. Whereas Hu teaches that a data identification unit (i.e. 202, 204, 206, 208 and 210. fig. 2B, see pars. [0007]) which identifies an input data signal input to the output terminal (i.e. the signal transmission line 112, fig. 2B, see the Abstract and par. [0043]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit apparatus of Joukou by incorporating the data identification unit of Hu to help identify the different types of signals transmitted on the same transmission circuit between the controller and the power conversion circuits.
In re to claim 19, Joukou disclose the power conversion circuit (i.e. fig. 1, see par. [0039]) according to claim 16, wherein the output signal includes an alarm signal (i.e. a protection alarm signal FO (Fault Out), see par. [0044] indicating whether the power conversion circuit is put into a preset state (i.e. see pars. [0044-0046]).
In re to claim 20, Joukou disclose the power conversion circuit (i.e. fig. 1, see par. [0039]) circuit according to claim 16, wherein the output signal includes an output data signal output by the power conversion circuit (i.e. power source circuit 11 extracts electric energy from the driving control signal CS transmitted from the interface circuit 2, and supplies a power source voltage to respective circuits provided within the IPM 3. In addition, the driving control signal CS transmitted from the interface circuit 2 is outputted to a driver circuit 22 via the AND gate 12, the photocoupler 31, and an AND gate 21, see fig. 1 and par. [0044]).
Claims 9 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Joukou et al. (US 2006/0193091 A1), hereinafter Joukou’ in view of Hu (US 2005/0168511 A1) and in view of Matsumoto et al. (US 6,420,962 B1), hereinafter Matsumoto’.
In re to claim 9, Joukou disclose the circuit apparatus circuit (i.e. fig. 1, see par. [0039]) according to claim 1. Except, Joukou and Hu fail to explicitly disclose that wherein the power conversion circuit further includes a clock identification unit which separates a clock signal input to the control terminal from the control signal. Whereas Matsumoto teach that wherein the power conversion circuit further includes a clock identification unit which separates a clock signal input to the control terminal from the control signal (i.e. fig. 1, see col. 6, lines 30-43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the clock identification circuit to the circuit apparatus of Joukou and Hu to help on identifying different types of signal inputs to the controller circuit.
In re to claim 21, Joukou disclose the power conversion circuit (i.e. fig. 1, see par. [0039]) according to claim 16. Except, Joukou and Hu fail to explicitly disclose that further comprising: a clock identification unit which separates a clock signal input to the control terminal from the control signal. Whereas Matsumoto teach that a clock identification unit which separates a clock signal input to the control terminal from the control signal (i.e. fig. 1, see col. 6, lines 30-43). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the clock identification circuit of Matsumoto to the circuit apparatus of Joukou and Hu to help on identifying different types of signal inputs to the controller circuit.
Allowable Subject Matter
Claims 2, 3, 6-8, 10-15, 17, 18, 22 are objected to as being dependent upon a rejected
base claims but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In re to claim 2, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein a first superimposed signal in which the output signal and the input data signal are superimposed on each other is input to the data identification unit, and the data identification unit identifies the input data signal based on the first superimposed signal and the output signal”.
In re to claim 10, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein a second superimposed signal in which the control signal and the clock signal with an amplitude different from the control signal are superimposed on each other is input to the control terminal, and the clock identification unit separates the control signal from the clock signal based on an amplitude of each pulse included in the second superimposed signal.
In re to claim 17, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein a first superimposed signal in which the output signal and the input data signal are superimposed on each other is input to the data identification unit, and the data identification unit identifies the input data signal based on the first superimposed signal and the output signal”.
In re to claim 22, None of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein a second superimposed signal in which the control signal and the clock signal with an amplitude different from the control signal are superimposed on each other is input to the control terminal, and the clock identification unit separates the control signal from the clock signal based on an amplitude of each pulse included in the second superimposed signal”.
The art of record does not disclose the above limitations, nor would it be obvious to modify the art of record to include either of the above limitations.
In re to claims 3 and 6-8, claims 3 and 6-8 depend on claim 2, thus are also objected for the same reasons provided above.
In re to claims 11-15, claims 11-15 depend on claim 10, thus are also objected for the same reasons provided above.
In re to claim 18, claim 18 depend on claim 17, thus are also objected for the same reasons provided above.
Remarks
The examiner has cited columns, line numbers, paragraph numbers, references, or
figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YEMANE MEHARI whose telephone number is (571)270-7603. The examiner can normally be reached M-F 9AM TO 6 PM.
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/YEMANE MEHARI/Primary Examiner, Art Unit 2838