DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/27/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1 recites the limitation “if the capacitor is connected between thereof” in line 9 of the claim. This appears to mean “when the capacitor is connected between the first node and the input port”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claim(s) 1-3 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brauer et al. U.S. Patent Application 2012/0056655 (hereinafter “Brauer”).
Regarding claim 1, Brauer teaches a current limiter circuit (refer to figure 5)(refer also to [0006]), which limits a current in a path connecting an input terminal (i.e. IN)(fig.5) and an output terminal (i.e. OUT)(fig.5) through a switch (i.e. NMOS switch N0)(fig.5) including a control port (implicit), the switch controlling the current to a predetermined value or less (refer to [0043]), comprising: a controller (i.e. controller in the figure below)(fig.5), comprising a first input port (i.e. first input port in the figure below)(fig.5) which is connected to a connection point (i.e. connection point in the figure below)(fig.5) between a first path (i.e. first path in the figure below)(fig.5) through which a first signal (i.e. signal from current mirror 140)(fig.5) is transmitted (implicit) and a second path (i.e. second path in the figure below)(fig.5) through which a second signal (i.e. second signal in the figure below)(fig.5) is transmitted (implicit), and receives the first signal (implicit), and an output port (i.e. output in the figure below)(fig.5) which supplies a control signal combining the first signal and the second signal to a control port of the switch (implicit); and a negative feedback circuit (i.e. current mirror 140 and source follower 510)(fig.5), comprising an input port (i.e. input port in the figure below)(fig.5) coupled to a first node (i.e. first node in the figure below)(fig.5) via a capacitor (i.e. capacitor C)(fig.5) if the capacitor is connected between thereof (implicit) and the first node provided between the switch and the output terminal (implicit) and an output port connected to the first input port of the controller (implicit)(refer to drain of NMOS switch N2)(fig.5).
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Regarding claim 2, Brauer teaches the current limiter circuit according to claim 1, wherein the negative feedback circuit comprises a voltage-current conversion circuit (i.e. source follower 510)(fig.5) connected between a first input port of the controller and a second node (i.e. second node in the figure above)(fig.5) to which a first power supply voltage is supplied (implicit), and converting a voltage of an input port of the negative feedback circuit into a current based on a differential voltage between the voltage of the input port of the negative feedback circuit and the threshold voltage if the voltage of the input port of the negative feedback circuit is higher than a threshold voltage (refer to claims 10 and 11), and a clamp circuit (i.e. current mirror 140)(fig.5) connected between the input port of the negative feedback circuit and the second node (implicit), and clamping a voltage of the input port of the negative feedback circuit to the first power supply voltage or to a predetermined voltage higher than the first power supply voltage and lower than the threshold voltage (implicit).
Regarding claim 3, Brauer teaches the current limiter circuit according to claim 2, wherein the clamp circuit comprises a first constant current source (i.e. current mirror 140)(fig.5) which comprises a first port connected to the input port of the negative feedback circuit and a second port connected to the second node (implicit).
Regarding claim 15, Brauer teaches a current limiter device (refer to figure 5)(refer also to [0006]), comprising: an input terminal (i.e. IN)(fig.5); an output terminal (i.e. OUT)(fig.5); a switch (i.e. NMOS switch N0)(fig.5), comprising a control port (implicit), and limiting a current to a predetermined value or less (refer to [0043]); a capacitor (i.e. capacitor C)(fig.5), comprising a first end (implicit) connected to a first node (i.e. first node in the figure above)(fig.5) provided between the switch and the output terminal (implicit) and a second end (implicit); a controller (i.e. controller in the figure below)(fig.5), comprising a first input port (i.e. first input port in the figure above)(fig.5) which is connected to a connection point (i.e. connection point in the figure above)(fig.5) between a first path (i.e. first path in the figure above)(fig.5) through which a first signal (i.e. signal from current mirror 140)(fig.5) is transmitted (implicit) and a second path (i.e. second path in the figure above)(fig.5) through which a second signal (i.e. second signal in the figure above)(fig.5) is transmitted (implicit), and receives the first signal (implicit) and an output port (i.e. output in the figure above)(fig.5) which supplies a control signal combining the first signal and the second signal to a control port of the switch (implicit); and a negative feedback circuit (i.e. current mirror 140 and source follower 510)(fig.5), comprising an input port (i.e. input port in the figure above)(fig.5) coupled to the first node via the capacitor (implicit) in the case of being connected between to the second port of the capacitor (implicit) and an output port connected to the first input port of the controller (implicit)(refer to drain of NMOS switch N2)(fig.5).
Claim(s) 1, 2, 7, 9, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Robb U.S. Patent No. 6,781,502 (hereinafter “Robb”).
Regarding claim 1, Robb teaches a current limiter circuit (refer to figure 1)(refer also to col. 2 lines 50-62), which limits a current in a path connecting an input terminal (i.e. return 13)(fig.1) and an output terminal (i.e. return 17)(fig.1) through a switch (i.e. transistor 18)(fig.1) including a control port (implicit), the switch controlling the current to a predetermined value or less (refer to col. 2 lines 50-62), comprising: a controller (i.e. controller in the figure below)(fig.1), comprising a first input port (i.e. first input port in the figure below)(fig.1) which is connected to a connection point (i.e. connection point in the figure below)(fig.1) between a first path (i.e. first path in the figure below)(fig.1) through which a first signal (i.e. signal from transistor 19)(fig.1) is transmitted (implicit) and a second path (i.e. second path in the figure below)(fig.1) through which a second signal (i.e. second signal in the figure below)(fig.1) is transmitted (implicit), and receives the first signal (implicit), and an output port (i.e. output in the figure below)(fig.1) which supplies a control signal combining the first signal and the second signal to a control port of the switch (implicit); and a negative feedback circuit (i.e. resistor 22 and transistor 19)(fig.1), comprising an input port (i.e. input port in the figure below)(fig.1) coupled to a first node (i.e. first node in the figure below)(fig.1) via a capacitor (i.e. capacitor 21)(fig.1) if the capacitor is connected between thereof (implicit) and the first node provided between the switch and the output terminal (implicit) and an output port connected to the first input port of the controller (implicit).
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Regarding claim 2, Robb teaches the current limiter circuit according to claim 1, wherein the negative feedback circuit comprises a voltage-current conversion circuit (i.e. transistor 19)(fig.1) connected between a first input port of the controller and a second node (i.e. second node in the figure above)(fig.1) to which a first power supply voltage is supplied (implicit), and converting a voltage of an input port of the negative feedback circuit into a current based on a differential voltage between the voltage of the input port of the negative feedback circuit and the threshold voltage if the voltage of the input port of the negative feedback circuit is higher than a threshold voltage (implicit), and a clamp circuit (i.e. resistor 22)(fig.1) connected between the input port of the negative feedback circuit and the second node (implicit), and clamping a voltage of the input port of the negative feedback circuit to the first power supply voltage or to a predetermined voltage higher than the first power supply voltage and lower than the threshold voltage (implicit).
Regarding claim 7, Robb teaches the current limiter circuit according to claim 2, wherein the clamp circuit comprises a resistor (i.e. resistor 22)(fig.1) comprising a first end connected to the input port of the negative feedback circuit (implicit) and a second end connected to the second node (implicit).
Regarding claim 9, Robb teaches the current limiter circuit according to claim 2, wherein the voltage-current converter circuit comprises an FET (i.e. transistor 22)(fig.1) connected between the connection point and the second node (implicit), the FET comprising a gate connected to a first port of the clamp circuit (implicit)(refer to input port in the figure above)(fig.1).
Regarding claim 15, Robb teaches a current limiter device (refer to figure 1)(refer also to col. 2 lines 50-62), comprising an input terminal (i.e. return 13)(fig.1); an output terminal (i.e. return 17)(fig.1); a switch (i.e. transistor 18)(fig.1), comprising a control port (implicit) and limiting a current to a predetermined value or less (refer to col. 2 lines 50-62); a capacitor (i.e. capacitor 21)(fig.1), comprising a first end connected to a first node (i.e. first node in the figure above)(fig.1) provided between the switch and the output terminal (implicit) and a second end (implicit); a controller (i.e. controller in the figure above)(fig.1), comprising a first input port (i.e. first input port in the figure above)(fig.1) which comprises a connection point (i.e. connection point in the figure above)(fig.1) between a first path (i.e. first path in the figure above)(fig.1) through which a first signal (i.e. signal from transistor 19)(fig.1) is transmitted (implicit) and a second path (i.e. second path in the figure above)(fig.1) through which a second signal (i.e. second signal in the figure above)(fig.1) is transmitted (implicit), and receives the first signal (implicit) and an output port (i.e. output in the figure above)(fig.1) which supplies a control signal combining the first signal and the second signal to a control port of the switch (implicit); and a negative feedback circuit (i.e. resistor 22 and transistor 19)(fig.1), comprising an input port (i.e. input port in the figure above)(fig.1) coupled to the first node via the capacitor (implicit) in the case of being connected to the second port of the capacitor (implicit) and an output port (implicit) connected to the first input port of the controller (implicit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robb as applied to claim 2 above, and further in view of Farwell U.S. Patent No. 5,670,865 (hereinafter “Farwell”).
10. The current limiter circuit according to claim 2, wherein the voltage-current conversion circuit comprises an amplifier circuit comprising a first input port connected to a first port of the clamp circuit, a second input port receiving the threshold voltage, and an output port connected to the connection point, and supplying a current based on a differential voltage between a voltage of the first input port and the threshold voltage supplied to the second input port to the output port of the amplifier circuit.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robb as applied to claim 1 above, and further in view of Austruy et al. European Patent Document EP 0490010 A1 (hereinafter “Austruy”).
Regarding claim 12, Robb teaches the current limiter circuit according to claim 1; however, Robb does not teach wherein the controller comprises a second input port connected to the first node, a third input port connected to a third node provided between the switch and the input terminal, a voltage detection circuit comprising a first input port connected to the second input port of the controller, a second input port connected to the third input port of the controller, and an output port outputting a signal which comprises a plurality of signal levels and is based on a voltage difference between voltages respectively received at the first input port and the second input of the controller as the second signal, and an output port connected to the output port of the voltage detection circuit via the connection point. However, Austruy teaches wherein the controller comprises a second input port (refer to inverting input of operational amplifier 86)(fig.3) connected to the first node (i.e. node 98)(fig.3), a third input port (i.e. node 94)(fig.3) connected to a third node (i.e. node 104)(fig.3) provided between the switch and the input terminal (implicit), a voltage detection circuit (i.e. operational amplifier 86)(fig.3) comprising a first input port (i.e. inverting input of operational amplifier 86)(fig.3) connected to the second input port of the controller (implicit), a second input port (i.e. non-inverting input of operational amplifier 86)(fig.3) connected to the third input port of the controller (implicit), and an output port outputting a signal which comprises a plurality of signal levels and is based on a voltage difference between voltages respectively received at the first input port and the second input of the controller as the second signal (implicit), and an output port connected to the output port of the voltage detection circuit via the connection point (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Robb to include the controller of Austruy to provide the advantage of detecting connection of a hotswap.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Robb and Austruy as applied to claim 12 above, and further in view of Cao Chinese Patent Document CN 107565528 B (hereinafter “Cao”).
Regarding claim 13, Robb and Austruy teach the current limiter circuit according to claim 12, however, they do not teach the circuit further comprising a source-grounded amplifier circuit connected between the connection point and the output port of the controller, wherein the source-grounded amplifier circuit comprising an FET of which a gate receives a voltage of the connection point. However, Cao teaches the circuit further comprising a source-grounded amplifier circuit (i.e. transistor Q3)(fig.2) connected between the connection point and the output port of the controller (implicit), wherein the source-grounded amplifier circuit comprising an FET of which a gate receives a voltage of the connection point (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Robb and Austruy to include the amplifier circuit of Cao to provide the advantage of ensuring proper turn-on/off of the switch.
Regarding claim 14, Robb and Austruy teach the current limiter circuit according to claim 12, however, they do not teach the circuit further comprising a source follower circuit connected between the connection point and an output port of the controller, wherein the source follower circuit comprising an FET of which a gate receives a voltage of the connection point. However, Cao teaches the circuit further comprising a source follower circuit (i.e. transistor Q2)(fig.2) connected between the connection point and an output port of the controller (implicit), wherein the source follower circuit comprising an FET of which a gate receives a voltage of the connection point (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Robb and Austruy to include the source follower of Cao to provide the advantage of ensuring proper turn-on/off of the switch.
Allowable Subject Matter
Claims 4-6, 8, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 4 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 4, especially wherein the first constant current source comprises a depletion type field effect transistor (FET) with a source and a gate connected.
Claim 5 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially wherein the first constant current source comprises a first FET comprising a drain connected to the input port of the negative feedback circuit, a source connected to the second node, and a gate, a second FET comprising a drain connected to the gate of the first FET, a source connected to the second node, and a gate connected to the gate of the first FET and the drain of the second FET, and a second constant current source supplying a constant current to the drain of the second FET.
Claim 6 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 6, especially wherein the clamp circuit comprises a bias circuit supplying the predetermined voltage to a node connecting the input port of the negative feedback circuit, the clamp circuit, and the voltage-current conversion circuit. Claim 8 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially wherein the clamp circuit comprises a resistor comprising a first end connected to the input port of the negative feedback circuit and a second end connected to the second node, and a bias circuit supplying the predetermined voltage to a node connecting the input port of the negative feedback circuit, the clamp circuit, and the voltage-current conversion circuit. Claim 11 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 11, especially wherein the voltage-current conversion circuit comprises an amplifier circuit comprising a first input port connected to a first port of the clamp circuit, a second input port receiving the threshold voltage, a first output port connected to the connection point, and a second output port, a voltage source comprising a control port receiving a switching signal for switching the threshold voltage as a first threshold voltage or a second threshold voltage, and an output port switching and outputting the threshold voltage by switching between the first threshold voltage and the second threshold voltage, and an output port switching the threshold voltage to be outputted as the first threshold voltage or the second threshold voltage based on the switching signal and outputting the same, and a switching signal generation circuit comprising an input port connected to the second output port of the amplifier circuit and an output port connected to the control port of the voltage source and outputting the switching signal, and generating the switching signal comprising two different signal levels corresponding to the magnitude of a current supplied to the input port.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838