97
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 recites the limitation "the second has table" in line 8. There is insufficient antecedent basis for this limitation in the claim. The examiner has treated this limitation as “the second hash table.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hendry et al., US PGPub 2011/0252180, hereafter “Hendry.”
With respect to claim 9, Hendry teaches a computing system, comprising:
a memory (par. 43 and fig. 3, memory 14); and
a table remap circuit (par. 43 and fig. 3, memory controller 36), to modify a size of a table comprising table elements stored in the memory (par. 81 and fig. 11, memory mapping diagram 120), while the table is available for access by one or more users (par. 90, the remapping is done-on-the fly, allowing the memory controller 36 to perform other operations), by:
dividing the table into (i) a first part designated to store table elements that are to be removed from the table and (ii) a second part designated to store table elements that are to be retained in the table (par. 81 and fig. 11, bank 2 is the first part and banks 0 and 1 comprise the second part);
iteratively transferring the table elements from the first part to the second part (par. 92 and fig. 11, the data is copied from bank 2 to locations in banks 0 and 1, while continuing to be accessible during the iterative remapping process); and
remapping the table to the second part of the table (par. 92, after the remapping is complete, bank 2 is shut down, meaning the table consists of just banks 0 and 1, the second part of the table).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-6, 8-12, 14-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hendry et al., US PGPub 2011/0252180, hereafter “Hendry,” in view of Gupta et al., US PGPub 2008/0098001, hereafter “Gupta.”
With respect to claim 1, Hendry teaches a computing system, comprising:
a memory (par. 43 and fig. 3, memory 14); and
a table remap circuit (par. 43 and fig. 3, memory controller 36), to modify a size of a table comprising table elements stored in the memory (par. 81 and fig. 11, memory mapping diagram 120), while the table is available for access by one or more users (par. 90, the remapping is done-on-the fly, allowing the memory controller 36 to perform other operations), by:
defining a first interim table and a second interim table (par. 81 and fig. 11, bank 2 is the first interim table and banks 0 and 1 comprise the second interim table);
iteratively transferring table elements from the first interim table to the second interim table (par. 92 and fig. 11, the data is copied from bank 2 to locations in banks 0 and 1, while continuing to be accessible during the iterative remapping process);
in response to a request from a user to write a table element in the table, writing the table element in the first interim table or in the second interim table in accordance with a selection criterion (par. 90, “From the perspective of the OS, the OS is merely employing a reduced address space. Indeed, all reads and writes may occur as expected while the transition from the three-bank memory mapping to the two-bank memory mapping is taking place. In this way, the memory may be remapped dynamically and on-the-fly without excessive copying. Thus, if the memory controller 36 needs to perform other operations on the memory stored in the memory banks 40 for another purpose, the copying of block 130 may pause while the memory controller 36 performs such other operations. When the other operations have ended, the atomic copying of block 130 may continue until complete.” The reads and writes that occur during the remapping process will be subject to a selection criterion of whether the address has been remapped or not. If the address has not been remapped, a write will occur to bank 2, while if it has been remapped, the write will occur to bank 0/1); and
remapping the table to the second interim table (par. 92, after the remapping is complete, bank 2 is shut down, meaning the table consists of just banks 0 and 1, the second interim table).
Hendry fails to teach that the selection criterion depends on a data value of the table element to be written.
Gupta teaches a selection criterion that depends on a data value of the table element to be written (pars. 86-88 describe a remap process that adds new entries to the hash table gradually as they are processed, and selects the hash table when processing values that are already populated to it).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendry and Gupta before him before the earliest effective filing date, to modify the table remap circuit of Hendry with the table remap circuit of Gupta, in order to remap by gradually populating a hash table as chunks are processed, thereby deferring the resource usage of a fully populated hash table.
With respect to claim 2, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the computing system according to claim 1, wherein the first interim table is part of the table (par. 81 and fig. 11, bank 2 is the first interim table, which is part of table 120).
With respect to claim 3, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the computing system according to claim 1, wherein the second interim table is part of the table (par. 81 and fig. 11, banks 0 and 1 comprise the second interim table, which is part of table 120).
With respect to claim 5, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the computing system according to claim 1, wherein the table remap circuit is to respond to a request from the user to read a table element that corresponds to a given match key by: if the second interim table contains a table element corresponding to the given match key, providing the user with the table element from the second interim table; and if no table element from the second interim table corresponds to the given match key, providing the user with a table element from the first interim table that corresponds to the match key (par. 90, “From the perspective of the OS, the OS is merely employing a reduced address space. Indeed, all reads and writes may occur as expected while the transition from the three-bank memory mapping to the two-bank memory mapping is taking place. In this way, the memory may be remapped dynamically and on-the-fly without excessive copying. Thus, if the memory controller 36 needs to perform other operations on the memory stored in the memory banks 40 for another purpose, the copying of block 130 may pause while the memory controller 36 performs such other operations. When the other operations have ended, the atomic copying of block 130 may continue until complete.” The reads and writes that occur during the remapping process will be subject to a selection criterion of whether the address has been remapped or not. If the address has not been remapped, a read will occur from bank 2, while if it has been remapped, the read will occur from bank 0/1).
With respect to claim 6, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the computing system according to claim 1, wherein the table remap circuit comprises an iterator circuit for iteratively scanning tables in the memory, and wherein the table remap circuit is to transfer the table elements from the first interim table to the second interim table by scanning the first interim table using the iterator circuit (par. 92, which describes copying from bank 2 to the other active banks, with possible intervening operations occurring during the copying, meaning the copy is an iterative process).
With respect to claim 8, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the computing system according to claim 1, wherein the table elements comprise pointers to allocated memory segments (par. 92, the DIMM addresses are pointers to physical address of memory).
With respect to claim 10, Hendry teaches a computing method, comprising:
modifying a size of a table comprising table elements stored in a memory (par. 81 and fig. 11, memory mapping diagram 120), while the table is available for access by one or more users (par. 90, the remapping is done-on-the fly, allowing the memory controller 36 to perform other operations), by:
defining a first interim table and a second interim table (par. 81 and fig. 11, bank 2 is the first interim table and banks 0 and 1 comprise the second interim table);
iteratively transferring table elements from the first interim table to the second interim table (par. 92 and fig. 11, the data is copied from bank 2 to locations in banks 0 and 1, while continuing to be accessible during the iterative remapping process);
in response to a request from a user to write a table element in the table, writing the table element in the first interim table or in the second interim table in accordance with a selection criterion (par. 90, “From the perspective of the OS, the OS is merely employing a reduced address space. Indeed, all reads and writes may occur as expected while the transition from the three-bank memory mapping to the two-bank memory mapping is taking place. In this way, the memory may be remapped dynamically and on-the-fly without excessive copying. Thus, if the memory controller 36 needs to perform other operations on the memory stored in the memory banks 40 for another purpose, the copying of block 130 may pause while the memory controller 36 performs such other operations. When the other operations have ended, the atomic copying of block 130 may continue until complete.” The reads and writes that occur during the remapping process will be subject to a selection criterion of whether the address has been remapped or not. If the address has not been remapped, a write will occur to bank 2, while if it has been remapped, the write will occur to bank 0/1); and
remapping the table to the second interim table (par. 92, after the remapping is complete, bank 2 is shut down, meaning the table consists of just banks 0 and 1, the second interim table).
Hendry fails to teach that the selection criterion depends on a data value of the table element to be written.
Gupta teaches a selection criterion that depends on a data value of the table element to be written (pars. 86-88 describe a remap process that adds new entries to the hash table gradually as they are processed, and selects the hash table when processing values that are already populated to it).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendry and Gupta before him before the earliest effective filing date, to modify the table remap circuit of Hendry with the table remap circuit of Gupta, in order to remap by gradually populating a hash table as chunks are processed, thereby deferring the resource usage of a fully populated hash table.
With respect to claim 11, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the method according to claim 10, wherein the first interim table is part of the table (par. 81 and fig. 11, bank 2 is the first interim table, which is part of table 120).
With respect to claim 12, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the method according to claim 10, wherein the second interim table is part of the table (par. 81 and fig. 11, banks 0 and 1 comprise the second interim table, which is part of table 120).
With respect to claim 14, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the method according to claim 10, further comprising responding to a request from the user to read a table element that corresponds to a given match key by: if the second interim table contains a table element corresponding to the given match key, providing the user with the table element from the second interim table; and if no table element from the second interim table corresponds to the given match key, providing the user with a table element from the first interim table that corresponds to the match key (par. 90, “From the perspective of the OS, the OS is merely employing a reduced address space. Indeed, all reads and writes may occur as expected while the transition from the three-bank memory mapping to the two-bank memory mapping is taking place. In this way, the memory may be remapped dynamically and on-the-fly without excessive copying. Thus, if the memory controller 36 needs to perform other operations on the memory stored in the memory banks 40 for another purpose, the copying of block 130 may pause while the memory controller 36 performs such other operations. When the other operations have ended, the atomic copying of block 130 may continue until complete.” The reads and writes that occur during the remapping process will be subject to a selection criterion of whether the address has been remapped or not. If the address has not been remapped, a read will occur from bank 2, while if it has been remapped, the read will occur from bank 0/1).
With respect to claim 15, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the method according to claim 10, wherein transferring the table elements from the first interim table to the second interim table comprises scanning the first interim table using an iterator circuit (par. 92, which describes copying from bank 2 to the other active banks, with possible intervening operations occurring during the copying, meaning the copy is an iterative process).
With respect to claim 17, Hendry and Gupta teach all limitations of the parent claim. Hendry further teaches the method according to claim 10, wherein the table elements comprise pointers to allocated memory segments (par. 92, the DIMM addresses are pointers to physical address of memory).
Claim(s) 4, 7, 13, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hendry and Gupta, as applied to claims 1 and 10 above, in view of Behm et al., US Patent 11,481,398, hereafter “Behm.”
With respect to claim 4, Hendry and Gupta teach all limitations of the parent claim, but fail to teach wherein the tables are manages as LIFO data structures. Behm further teaches the computing system according to claim 1, wherein the table remap circuit is to manage each of (i) the table (ii) the first interim table, and (iii) the second interim table, as a respective Last-In First-Out (LIFO) data structure (col. 11, line 58, through col. 12, line 16, the grouping hash table, the partition p1, and the partition p2 are optionally managed as LIFOs).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendy, Gupta and Behm before him before the earliest effective filing date, to modify the table resize system of Hendy and Gupta with the table resize system of Behm, in order to improve processing speed, reduce transfer time and make efficient use of existing memory, as taught by Behm in col. 6, lines 59-63.
With respect to claim 7, Hendry and Gupta teach all limitations of the parent claim, but fails to teach that the table comprises a hash table. Behm further teaches the computing system according to claim 1, wherein the table comprises a hash table (col. 3, lines 51-55, a hash table is resized).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendy, Gupta and Behm before him before the earliest effective filing date, to modify the table resize system of Hendy and Gupta with the table resize system of Behm, in order to improve processing speed, reduce transfer time and make efficient use of existing memory, as taught by Behm in col. 6, lines 59-63.
With respect to claim 13, Hendry and Gupta teach all limitations of the parent claim, but fail to teach wherein the tables are managed as LIFO data structures. Behm further teaches the method according to claim 10, further comprising managing each of (i) the table (ii) the first interim table, and (iii) the second interim table, as a respective Last-In First-Out (LIFO) data structure (col. 11, line 58, through col. 12, line 16, the grouping hash table, the partition p1, and the partition p2 are optionally managed as LIFOs).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendy, Gupta and Behm before him before the earliest effective filing date, to modify the table resize system of Hendy and Gupta with the table resize system of Behm, in order to improve processing speed, reduce transfer time and make efficient use of existing memory, as taught by Behm in col. 6, lines 59-63.
With respect to claim 16, Hendry and Gupta teach all limitations of the parent claim, but fail to teach that the table comprises a hash table. Behm further teaches the method according to claim 10, wherein the table comprises a hash table (col. 3, lines 51-55, a hash table is resized).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendy, Gupta and Behm before him before the earliest effective filing date, to modify the table resize system of Hendy and Gupta with the table resize system of Behm, in order to improve processing speed, reduce transfer time and make efficient use of existing memory, as taught by Behm in col. 6, lines 59-63,
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hendry, in view of Behm.
With respect to claim 19, Hendry teaches a method for resizing a table comprising table elements stored in a memory, the method comprising:
defining a first table and a second table, wherein the second table is to contain the resized table following the resizing (par. 81 and fig. 11, bank 2 is the first table and banks 0 and 1 comprise the second table, and when the number of active memory banks is reduced to 2, the resized table comprises banks 0 and 1);
defining the first table as an inactive table and the second table as an active table (par. 83, and fig. 1, bank 2 contains the inactive addresses 16-23, and thus comprises an inactive table, and banks 0 and 1 contain the active addresses, and is thus an active table);
responding to user requests to access the table, by:
responding to a request to write a table element by writing the table element to the active table (par. 90, data is written to both the three-bank DIMM addresses and the two-bank DIMM addresses); and
responding to a request to read a table element, or to remove a table element, by reading or removing the table element from the active or inactive table, depending on a location of the table element (par. 90, “From the perspective of the OS, the OS is merely employing a reduced address space. Indeed, all reads and writes may occur as expected while the transition from the three-bank memory mapping to the two-bank memory mapping is taking place. In this way, the memory may be remapped dynamically and on-the-fly without excessive copying. Thus, if the memory controller 36 needs to perform other operations on the memory stored in the memory banks 40 for another purpose, the copying of block 130 may pause while the memory controller 36 performs such other operations. When the other operations have ended, the atomic copying of block 130 may continue until complete.” The reads and writes that occur during the remapping process will be subject to a selection criterion of whether the address has been remapped or not. If the address has not been remapped, a read will occur from bank 2, while if it has been remapped, the read will occur from bank 0/1); and
concurrently with responding to the user requests, performing an iterative process that gradually moves table elements from the inactive table to the active table (par. 92 and fig. 11, the data is copied from bank 2 to locations in banks 0 and 1, while continuing to be accessible during the iterative remapping process).
Hendry fails to teach that the table, first table, and second table are hash tables. Behm teaches the table is a hash table, the first table is a first hash table, and the second table is a second hash table (col. 11, line 58, through col. 12, line 16, the grouping hash table is the hash table, the partition p1 is the first hash table, and the partition p2 is the second hash table).
It would have been obvious to one of ordinary skill in the art, having the teachings of Hendy and Behm before him before the earliest effective filing date, to modify the table resize system of Hendy with the table resize system of Behm, in order to improve processing speed, reduce transfer time and make efficient use of existing memory, as taught by Behm in col. 6, lines 59-63.
Allowable Subject Matter
Claim 18 is allowed.
The following is an examiner’s statement of reasons for allowance: No prior art of record teaches “defining a "Do not Return to LIFO" (DTRL) threshold that distinguishes between (i) data values of table elements that are to be retained in the LIFO table following the resizing, and (ii) data values of table elements that are to be removed from the LIFO table following the resizing; and while the LIFO table is available for access by one or more users, performing an iterative process comprising, in each iteration: scanning the first table until identifying a first table element whose data value is greater than or equal to the DTRL threshold; scanning the second table until identifying a second table element whose data value is smaller than the DTRL threshold; and swapping the first table element and the second table element,” in combination with the rest of the claim limitations.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 12/02/2025 have been fully considered but they are not persuasive. With respect to independent claims 1 and 10, Applicant argues on pages 7-8 that Hendry fails to teach “a selection criterion that depends on a data value of the table element to be written.” These arguments are moot, as the new Gupta reference has been supplied to teach this limitation.
Applicant argues on pages 9-10 that Hendry fails to teach “dividing the table into (i) as a first part designated to store table elements that are to be removed from the table,” as allegedly, in Hendry, all data is retained in memory during and after the remapping process and no data is removed from memory. However, in the argument, applicant cites fig. 11 and par. 86 which clearly recite that bank 2 is a soon-to-be shut down memory bank and the data is copied from bank 2 into banks 0 and 1, which means data is removed from bank 2, which the examiner has mapped to the claimed table that has elements removed from.
Applicant’s arguments on page 10 with respect to dependent claims 4, 7, 13 and 16 are based on their dependence on the parent claim, and are moot, as the rejection of the parent claims are maintained.
Applicant’s arguments on pages 10-12, regarding amended claim 18, are persuasive, and the rejection of claim 18 is withdrawn.
Applicant’s arguments on pages 12-13, regarding claim 19, allege that Hendry and Behm fail to teach defining the first hash table as an inactive hash table and the second has[h] table as an active hash table, as the banks of Hendry’s memory are allegedly constantly active. However, bank 2 of Hendry, which corresponds to the inactive table, contains inactive addresses, as disclosed in par. 83, and thus could reasonably interpreted to be an “inactive table.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132