Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/6/2026 has been entered.
Response to Amendment
This Office action is in response to Applicant' s communication filed 8/6/2026 in response to the Office action dated 6/9/2026. Claims 1 and 9 have been amended. Claims 3 and 11 have been cancelled. Claims 1, 4-9, and 12-19 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 9, and 12-15 are rejected under 35 U.S.C 103 as being unpatentable over Olgiati (US 9858199 B1) in view of Lin et al. (US 20070106835 A1), hereinafter Lin, and further in view of Loh (US 20200183848 A1) and Buller (US 20210216404 A1).
Regarding claim 1, Olgiati teaches a method comprising: assigning a first address range and a second address range to a same physical memory device (Col. 5, line 63 – Col. 6, line 3; Fig. 3, virtual address spaces 300, 302 are mapped to the same physical memory 304),
wherein the first address range and the second address range are accessible by a same processing unit (Col. 3, line 60 – Col. 4, line 10; Col. 5, line 63 – Col. 6, line 3; Figs. 1 and 3, virtual address spaces 300, 302 are used by processes executed on a processor 102),
such that a region of the physical memory device is accessible using addresses within the first address range and using addresses within the second address range (Col. 6, lines 16-35; Fig. 3, shared physical memory region 316 is accessed by first shared virtual address region 310 of first virtual address space 300 and second shared virtual address region 312 of second virtual address space 302); and
allocating a first portion of the physical memory device to the first address range for storage (Col. 5, line 63 – Col. 6, line 15; Fig. 3, allocating to first virtual address space 300 which maps to portions of physical memory 304).
Olgiati does not explicitly teach creating an executable file using a linker script, the first address range for storage of instructions, starting at a first starting address, using the linker script to determine which functions are to be stored in the first portion of the physical memory device; determining a size of the first portion, referred to as an offset, after the determination has been made; adding the offset to a starting address of the second address range to define a new second address of the second address range; allocating data in the physical memory device to the second address range starting at the new second address of the second address range; wherein the allocating, determining, and adding are performed by the linker script, and allocates instructions starting at the first starting address in the first address range and data starting at the new second address in the second address range.
However, Lin teaches determining which functions are to be stored in the first portion of the physical memory device (Paragraphs 20, 31; Fig. 3, controller 315 accesses the memory device and determines to prevent storing parameters and store only program code into the program code block [first portion]);
a first address range for storage of instructions (Paragraphs 21-22; Table 1, first address range 0x00000 – 0x0FFFF stores program code [instructions]), and
allocating instructions in the first address range (Paragraphs 21-22, allocating program codes [instructions] to the first address range 0x00000 – 0x0FFFF).
Olgiati and Lin are analogous art because they are in the same field of endeavor, that being allocation of specific address spaces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Loh to further include the allocation/storage of instructions according to the teachings of Lin. The motivation for doing so would have been to reduce cost and increase access speed by storing both code/instructions and data into a single memory device (Lin, Paragraph 10).
Olgiati in view of Lin does not explicitly teach creating an executable file using a linker script, a first address range starting at a first starting address, using the linker script to determine which functions are to be stored; determining a size of the first portion, referred to as an offset, after the determination has been made; adding the offset to a starting address of the second address range to define a new second address of the second address range; allocating data in the physical memory device to the second address range starting at the new second address of the second address range; wherein the allocating, determining, and adding are performed by the linker script, and allocates starting at the first starting address in the first address range and data starting at the new second address in the second address range.
However, Loh teaches a first address range starting at a first starting address (Paragraph 31; Fig. 1, region 140 starting at address 142 [first starting address]),
determining a size of the first portion, referred to as an offset (Paragraphs 35, 48; Fig. 1, cache controller implements region parameters 150, which includes the size parameter 158 (S bytes) of the region 140)
after the determination has been made (Paragraphs 27-28, updating parameters including a region size [determining a size of the first portion] after the determination to store data);
adding the offset to a starting address of the second address range to define a new second address of the second address range (Paragraph 37; Fig. 1, adding S bytes [offset] to address 142 [starting second address] obtains the starting address [new second address] for the region after region 140);
allocating data in the physical memory device to the second address range starting at the new second address of the second address range (Paragraphs 31 and 33; Fig. 1, region after region 140 [second address range] stores data starting at address 142 + S bytes [new second address]); and
allocates starting at the first starting address in the first address range (Paragraph 31; Fig. 1, storing data in region 140 starting at address 142) and
data starting at the new second address in the second address range (Paragraphs 31 and 33; Fig. 1, storing data in region after region 140 starting at address 142 + S bytes).
Olgiati, Lin, and Loh are analogous art because they are in the same field of endeavor, that being allocation of specific address spaces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Lin to further include the address management according to the teachings of Loh. The motivation for doing so would have been to improve lookup operation speed (Loh, Paragraph 29).
Olgiati in view of Lin, further in view of Loh does not explicitly teach creating an executable file using a linker script, using the linker script to determine which functions are to be stored, and wherein the allocating, determining, and adding are performed by the linker script.
However, Buller teaches creating an executable file using a linker script (Paragraph 24; Fig. 1, a linker script is used to compile software applications/programs (such as an executable file) for computing system 100),
using the linker script to determine which functions are to be stored (Paragraphs 24-25; Fig. 1, a compiler, including the linker script, allocates software programs to address spaces in RAM 170);
wherein the allocating, determining, and adding are performed by the linker script (Paragraphs 24-25, 59, 62; Figs. 1 and 6, steps 610-620, the linker script manages data accesses and RAM 170 address spaces [allocating], determines an offset and RAM address space to use [determining], and specifies the base offset register to which accesses may be performed [adding]).
Olgiati, Lin, Loh, and Buller are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Lin, further in view of Loh to further include the linker script according to the teachings of Buller. The motivation for doing so would have been to improve overall memory performance during virtual memory resolution by using a linker script to specify a fixed PIC base register (Buller, Paragraphs 59, 62).
Regarding claim 4, Olgiati in view of Loh, further in view of Buller teaches the method of claim 1, but does not explicitly teach wherein the first address range is designated as read only.
However, Lin teaches wherein the first address range is designated as read only (Paragraph 22; Table 1, first address range 0x00000 – 0x0FFFF containing program code is read-only).
Olgiati, Loh, Buller, and Lin are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Loh, further in view of Buller to further include the read-only address range according to the teachings of Lin. The motivation for doing so would have been to reduce the cost of the memory system by emulating the function of an external read-only memory (Lin, Paragraphs 5 and 10).
Regarding claim 5, Olgiati in view of Lin, further in view of Loh and Buller teaches the method of claim 1, wherein the second address range is designated as readable and writable (Lin, Paragraph 22; Table 1, Fig. 3, second address range 0x10000 – 0x17FFF is read and written by MCU 114).
Regarding claim 6, Olgiati in view of Lin, further in view of Loh and Buller teaches a system comprising: a processing unit (Loh, Paragraphs 31 and 40, processing units execute the embodiment of data storage 100);
a nonvolatile memory device (Loh, Paragraphs 31-32; Fig. 1, system memory 110 includes one or more hard disk drives and solid-state disks [non-volatile memory]);
and the physical memory device configured by executing the executable file created using the method of claim 1 (Buller, Paragraphs 21, 24; Fig. 1, a linker script is used to compile software applications/programs (such as an executable file) for computing system 100 which includes memory 170);
wherein the processing unit uses the first address range to access instructions and the second address range to access data (Lin, Paragraphs 19, 22; Table 1, Fig. 3, MCU 114 (Micro Computer Unit) [processing unit] reads program codes [instructions] in first address range 0x00000 – 0x0FFFF and reads/writes data in second address range 0x18000 – 0x1FFFF).
Regarding claim 7, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 6, wherein the nonvolatile memory device contains instructions (Lin, Paragraph 22; Table 1, Fig. 3, embedded non-volatile memory 312 stores program codes [instructions] at address range 0x00000 – 0x0FFFF).
Regarding claim 9, Olgiati teaches a method comprising: assigning a first address range and a second address range to a same physical memory device (Col. 5, line 63 – Col. 6, line 3; Fig. 3, virtual address spaces 300, 302 are mapped to the same physical memory 304),
wherein the first address range and the second address range are accessible by a same processing unit (Col. 3, line 60 – Col. 4, line 10; Col. 5, line 63 – Col. 6, line 3; Figs. 1 and 3, virtual address spaces 300, 302 are used by processes executed on a processor 102),
such that a region of the physical memory device is accessible using addresses within the first address range and using addresses within the second address range (Col. 6, lines 16-35; Fig. 3, shared physical memory region 316 is accessed by first shared virtual address region 310 of first virtual address space 300 and second shared virtual address region 312 of second virtual address space 302); and
allocating a first portion of the physical memory device to the second address range for storage (Col. 5, line 63 – Col. 6, line 15; Fig. 3, second virtual address space 302 maps to portions of physical memory 304).
Olgiati does not explicitly teach creating an executable file using a linker script, the second address range for storage of a first portion of data, starting at a second starting address; determining a size of the first portion of data, referred to as a first offset; adding the first offset to a starting address of the first address range to define a new first address of the first address range; allocating a second portion of the physical memory device to the first address range for storage of instructions, starting at the new first address; using the linker script to determine which functions are to be stored in the second portion of the memory device; determining a size of the instructions, referred to as a second offset after the determination has been made; adding the second offset to an ending address of the first portion of data to define a new second address; allocating a second portion of data to the second address range starting at the new second address of the second address range; wherein the allocating, determining, and adding are performed by the linker script; and allocates instructions starting at the new first address, a first portion of data starting at the second starting address and a second portion of data starting at the new second address.
However, Lin teaches a first address range for storage of instructions (Paragraphs 21-22; Table 1, first address range 0x00000 – 0x0FFFF stores program code [instructions]),
determining which functions are to be stored in the second portion of the memory device (Paragraphs 20, 31; Fig. 3, controller 315 accesses the memory device and determines to prevent storing parameters and store only program code into the program code block [second portion]), and
allocates instructions starting at the new first address (Paragraphs 21-22, allocating program codes [instructions] to the first address range starting at 0x00000).
Olgiati and Lin are analogous art because they are in the same field of endeavor, that being allocation of specific address spaces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati to further include the allocation/storage of instructions according to the teachings of Lin. The motivation for doing so would have been to reduce cost and increase access speed by storing both code/instructions and data into a single memory device (Lin, Paragraph 10).
Olgiati in view of Lin does not explicitly teach creating an executable file using a linker script, the second address range for storage of a first portion of data, starting at a second starting address; determining a size of the first portion of data, referred to as a first offset; adding the first offset to a starting address of the first address range to define a new first address of the first address range; allocating a second portion of the physical memory device to the first address range for storage, starting at the new first address; using a linker script to determine which functions are to be stored; determining a size of the instructions, referred to as a second offset after the determination has been made; adding the second offset to an ending address of the first portion of data to define a new second address; allocating a second portion of data to the second address range starting at the new second address of the second address range; wherein the allocating, determining, and adding are performed by the linker script; and allocates starting at the new first address, a first portion of data starting at the second starting address and a second portion of data starting at the new second address.
However, Loh teaches a second address range for storage of a first portion of data, starting at a second starting address (Paragraphs 61-62; Fig. 5, region 126 [part of second address range] stores data [first portion of data] starting at address 142 [second starting address]);
determining a size of the first portion of data, referred to as a first offset (Paragraphs 48, 50, 62; Fig. 5, cache controller implements the functionality of [determines] region parameters 150, which include the size 158 (S bytes) of the region 126);
adding the first offset to a starting address of the first address range to define a new first address of the first address range (Paragraphs 61-62; Fig. 5, adding S bytes [first offset] to address 142 [starting first address] obtains the starting address [new first address] of added region 526 [first address range]);
allocating a second portion of the physical memory device to the first address range for storage, starting at the new first address (Paragraphs 61-62; Fig. 5, region 526 [second portion of the physical device] stores data starting at address 142 + S bytes [new first address]);
determining a size of the instructions, referred to as a second offset (Paragraphs 48, 50, 62; Fig. 5, cache controller implements the functionality of [determines] region parameters 150, which include the size 158 (T bytes) of the region 526)
after the determination has been made (Paragraphs 27-28, updating parameters including a region size [determining a size of the instructions] after the determination to store data);
adding the second offset to an ending address of the first portion of data to define a new second address (Paragraphs 61-62; Fig. 5, adding T bytes [second offset] to address 142 + S bytes [ending address of first portion] obtains the starting address [new second address] for the region after added region 526);
allocating a second portion of data to the second address range starting at the new second address of the second address range (Paragraphs 61-62; Fig. 5, region after added region 526 stores data [second portion of data] starting at address 142 + S + T bytes [new second address]); and
allocates starting at the new first address (Paragraphs 61-62; Fig. 5, storing data starting at address 142 + S bytes),
a first portion of data starting at the second starting address (Paragraphs 61-62; Fig. 5, storing [first] data starting at address 142),
and a second portion of data starting at the new second address (Paragraphs 61-62; Fig. 5, storing [second] data starting at address 142 + S + T bytes).
Olgiati, Lin, and Loh are analogous art because they are in the same field of endeavor, that being allocation of specific address spaces. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Lin to further include the address management according to the teachings of Loh. The motivation for doing so would have been to improve lookup operation speed (Loh, Paragraph 29).
Olgiati in view of Lin, further in view of Loh does not explicitly teach creating an executable file using a linker script, using a linker script to determine which functions are to be stored; and wherein the allocating, determining, and adding are performed by the linker script.
However, Buller teaches creating an executable file using a linker script (Paragraph 24; Fig. 1, a linker script is used to compile software applications/programs (such as an executable file) for computing system 100),
using the linker script to determine which functions are to be stored (Paragraphs 24-25; Fig. 1, a compiler, including the linker script, allocates software programs to address spaces in RAM 170);
wherein the allocating, determining, and adding are performed by the linker script (Paragraphs 24-25, 59, 62; Figs. 1 and 6, steps 610-620, the linker script manages data accesses and RAM address spaces [allocating], determines an offset and RAM 170 address space to use [determining], and specifies the base offset register to which accesses may be performed [adding]).
Olgiati, Lin, Loh, and Buller are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Lin, further in view of Loh to further include the linker script according to the teachings of Buller. The motivation for doing so would have been to improve overall memory performance during virtual memory resolution by using a linker script to specify a fixed PIC base register (Buller, Paragraphs 59, 62).
Regarding claim 12, Olgiati in view of Loh, further in view of Buller teaches the method of claim 9, but does not explicitly teach wherein the first address range is designated as read only.
However, Lin teaches wherein the first address range is designated as read only (Paragraph 22; Table 1, first address range 0x000000 – 0x0FFFF containing program code is read-only).
Olgiati, Loh, Buller, and Lin are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Olgiati in view of Loh, further in view of Buller to further include the read-only address range according to the teachings of Lin. The motivation for doing so would have been to reduce the cost of the memory system by emulating the function of an external read-only memory (Lin, Paragraphs 5 and 10).
Regarding claim 13, Olgiati in view of Lin, further in view of Loh and Buller teaches the method of claim 9, wherein the second address range is designated as readable and writable (Lin, Paragraph 22; Table 1, second address range 0x100000 – 0x17FFF is read and written by MCU 114).
Regarding claim 14, Olgiati in view of Lin, further in view of Loh and Buller teaches a system comprising: a processing unit (Loh, Paragraphs 31 and 40, processing units execute the embodiment of data storage 100);
a nonvolatile memory device (Loh, Paragraphs 31-32; Fig. 1, system memory 110 includes one or more hard disk drives and solid-state disks [non-volatile memory]);
and the physical memory device configured by executing the executable file created using the method of claim 9 (Buller, Paragraphs 21, 24; Fig. 1, a linker script is used to compile software applications/programs (such as an executable file) for computing system 100 which includes memory 170);
wherein the processing unit uses the first address range to access instructions and the second address range to access data (Lin, Paragraphs 19, 22; Table 1, Fig. 3, MCU 114 (Micro Computer Unit) [processing unit] reads program codes [instructions] in first address range 0x00000 – 0x0FFFF and reads/writes data in second address range 0x18000 – 0x1FFFF).
Regarding claim 15, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 14, wherein the nonvolatile memory device contains instructions (Lin, Paragraph 22; Table 1, Fig. 3, embedded non-volatile memory 312 stores program codes [instructions] at address range 0x00000 – 0x0FFFF).
Claims 8 and 16 are rejected under 35 U.S.C 103 as being unpatentable over Olgiati in view of Lin, further in view of Loh and Buller as applied to claims 6 and 14 above, and further in view of Li (US 20210034364 A1).
Regarding claim 8, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 6, but does not explicitly teach wherein the processing unit comprises separate buses for accessing instructions and data.
However, Li teaches wherein the processing unit comprises separate buses for accessing instructions and data (Paragraph 28; Fig. 1, processor core 110 uses bus 140 to store [access] only instruction information in instruction memory 120 and bus 150 to store only data information in data memory 130).
Olgiati, Lin, Loh, Buller, and Li are analogous art because they are in the same field of endeavor, that being memory segmentation and allocation. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olgiati in view of Lin, further in view of Loh and Buller to further include the separate buses for accessing instructions and data according to the teachings of Li. The motivation for doing so would have been to allow the fetching of instructions and data in the same clock cycle, increasing the execution efficiency of the processor (Li, Paragraphs 103-104).
Regarding claim 16, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 14, but does not explicitly teach wherein the processing unit comprises separate buses for accessing instructions and data.
However, Li teaches wherein the processing unit comprises separate buses for accessing instructions and data (Paragraph 28; Fig. 1, processor core 110 uses bus 140 to store [access] only instruction information in instruction memory 120 and bus 150 to store only data information in data memory 130).
Olgiati, Lin, Loh, Buller, and Li are analogous art because they are in the same field of endeavor, that being memory segmentation and allocation. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olgiati in view of Lin, further in view of Loh and Buller to further include the separate buses for accessing instructions and data according to the teachings of Li. The motivation for doing so would have been to allow the fetching of instructions and data in the same clock cycle, increasing the execution efficiency of the processor (Li, Paragraphs 103-104).
Claim 17 is rejected under 35 U.S.C 103 as being unpatentable over Olgiati in view of Lin, further in view of Loh and Buller as applied to claim 14 above, and further in view of Ramanujan et al (US 20130268728 A1), hereinafter Ramanujan.
Regarding claim 17, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 14 and the second portion comprises data buffers (Loh, Paragraph 48; cache 330 includes buffers storing data).
Olgiati in view of Lin, further in view of Loh and Buller does not explicitly teach wherein the first portion of data comprises secure data and other information.
However, Ramanujan teaches wherein the first portion of data comprises secure data and other information (Paragraphs 91, 116; Fig. 2, secure data and other information is stored in NVRAM 173).
Olgiati, Lin, Loh, Buller, and Ramanujan are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olgiati in view of Lin, further in view of Loh and Buller to further include the secure data and other information according to the teachings of Ramanujan. The motivation for doing so would have been to store and protect sensitive system information (Ramanujan, Paragraph 91).
Claims 18-19 are rejected under 35 U.S.C 103 as being unpatentable over Olgiati in view of Lin, further in view of Loh and Buller as applied to claims 7 and 14 above, and further in view of Chitnis et al. (US 20240037028 A1), hereinafter Chitnis.
Regarding claim 18, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 7, the nonvolatile memory device (Loh, Paragraphs 31-32; Fig. 1, system memory 110 includes one or more hard disk drives and solid-state disks [non-volatile memory]), and
the physical memory device (Olgiati, Col. 3, lines 60-65; Fig. 1, physical memory 106).
Olgiati in view of Lin, further in view of Loh and Buller does not explicitly teach wherein the processing unit copies instructions from the nonvolatile memory device to the region in the physical memory device by accessing the region using the second address range and executes the instructions that were copied into the region by accessing the region using the first address range.
However, Chitnis teaches wherein the processing unit copies instructions from the nonvolatile memory device to the region in the physical memory device by accessing the region using the second address range (Paragraphs 36, 48; Figs. 3 and 5, step 340, the compiler receives shared code [instructions] and stores only one copy of the shared code within shared address space 504 [region] which is accessed by CPU2 load [second] address range 508)
and executes the instructions that were copied into the region by accessing the region using the first address range (Paragraphs 37, 48; Fig. 5, executing an application (including shared code [instructions]) by accessing the shared code stored in shared address space 504 [region] using CPU1 load [first] address range 506).
Olgiati, Lin, Loh, Buller, and Chitnis are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olgiati in view of Lin, further in view of Loh and Buller to further include the copying of instructions via the second address range and the execution of instructions via the first address range according to the teachings of Chitnis. The motivation for doing so would have been to save memory space by storing common code only once (Chitnis, Paragraph 48).
Regarding claim 19, Olgiati in view of Lin, further in view of Loh and Buller teaches the system of claim 14, the nonvolatile memory device (Loh, Paragraphs 31-32; Fig. 1, system memory 110 includes one or more hard disk drives and solid-state disks [non-volatile memory]), and
the physical memory device (Olgiati, Col. 3, lines 60-65; Fig. 1, physical memory 106).
Olgiati in view of Lin, further in view of Loh and Buller does not explicitly teach wherein the processing unit copies instructions from the nonvolatile memory device to the region in the physical memory device by accessing the region using the second address range and executes the instructions that were copied into the region by accessing the region using the first address range.
However, Chitnis teaches wherein the processing unit copies instructions from the nonvolatile memory device to the region in the physical memory device by accessing the region using the second address range (Paragraphs 36, 48; Figs. 3 and 5, step 340, the compiler receives shared code [instructions] and stores only one copy of the shared code within shared address space 504 [region] which is accessed by CPU2 load [second] address range 508)
and executes the instructions that were copied into the region by accessing the region using the first address range (Paragraphs 37, 48; Fig. 5, executing an application (including shared code [instructions]) by accessing the shared code stored in shared address space 504 [region] using CPU1 load [first] address range 506).
Olgiati, Lin, Loh, Buller, and Chitnis are analogous art because they are in the same field of endeavor, that being memory address management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Olgiati in view of Lin, further in view of Loh and Buller to further include the copying of instructions via the second address range and the execution of instructions via the first address range according to the teachings of Chitnis. The motivation for doing so would have been to save memory space by storing common code only once (Chitnis, Paragraph 48).
Response to Arguments
Applicant’s arguments (see pages 6-10 of the remarks) filed 8/6/2026, with respect to the rejections of claims 1 and 9 under 35 U.S.C 103 have been fully considered, but are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., performing the allocating, determining, and adding before run time/at link time) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, in response to applicant's argument that Olgiati, Loh, and Lin are nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Olgiati, Loh, and Lin are mainly concerned with memory mapping and allocation in addressed data storage, as outlined in the methods of claims 1 and 9.
Although the allocating, determining, and adding in Olgiati, Loh, and Lin are not specifically performed by a linker script, the steps of the references are implemented via code or programs executed in computer media. Buller modifies these references by implementing the code/programs related to allocating, determining, and adding via a linker script (Buller, Paragraphs 24-25, 59, 62; Fig. 6, steps 610-620, performing an allocation of programs, a determination of sizes of address spaces to utilize for storage of data, and an addition of an offset to an address/register using a compiler including a linker script). In response to the Applicant’s argument that Buller does not suggest perform/suggest the allocating, determining, and adding limitations, although Buller does not explicitly describe the detailed memory allocation/mapping of those limitations, Buller does indicate that a linker script of a compiler would be capable of performing related memory management operations. It would have been obvious to one having ordinary skill of the art to have implemented the memory mapping/allocation steps of Olgiati, Loh, and Lin using the linker script of Buller in order to improve memory resolution/relocation performance (Buller, Paragraphs 59, 62). Thus, the Examiner maintains the combination of Olgiati, Loh, Lin, and Buller.
The Applicant further argues that none of the cited references teach the amended limitations (or similar thereof): “using the linker script to determine which functions are to be stored in the (first/second) portion of the physical memory device, and determining a size of the (first portion/instructions), referred to as an offset, after the determination has been made”.
However, Lin teaches determining which data, specifically code/functions, to store in a portion of a memory device (Lin, Paragraphs 20, 31; Fig. 3, accessing non-volatile memory device 312 and determining to store only program code into the program code memory portion of non-volatile memory device 312 instead of parameters). Buller then teaches implementing this determination using a linker script (Buller, Paragraphs 24-25, a compiler including a linker script determines which memory portions are available for allocation of software programs). Finally, Loh teaches determining an offset based off of the size of stored data after the determination of storing data to the memory device (Loh, Paragraphs 27-28, 35; Fig. 1, determining/updating parameters 150, including a size 158 [offset] of region 140, after (determining to) store data to the region 140). The argument(s) above support this combination of references.
Accordingly, the Examiner argues that the combination of Olgiati, Lin, Loh, and Buller teach the contested limitations of claims 1 and 9 and further notes any other arguments with respect to claims 1 and 9 are consummate in scope with the arguments above. Thus, the Examiner maintains the rejections set forth above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137
Prosecution Insights