Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application claim of the priority date of 12/13/2023 of the foreign application REPUBLIC OF KOREA 10-2023-0180819 is noted and entered. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/28/2024 was filed after the mailing date of the application on 05/28/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “a support passing through the stack; and a plurality of second insulating patterns disposed on side surfaces of gate electrodes that face the support” which renders the claim indefinite because it is inconsistent with the specification. Paragraph 0054 of the specification describes a third insulating pattern disposed between the support and the side surfaces of the electrode portions, not a second insulating pattern as described in claim 9. For the purposes of examination, the examiner will proceed by interpreting “a plurality of second insulating patterns” of claim 9 to be “a plurality of third insulating patterns”.
Claims 10-11 are rejected as being dependent on, and failing to cure the deficiencies of, rejected independent claim 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-8, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al, US 20190326316 A1 (Son).
Regarding claim 1; Son teaches a three-dimensional memory device (vertical memory device, paragraph 0004) comprising:
a stack (See Son: First Version of Annotated Fig. 3A shared in this OA, described in paragraph 0025) including:
a plurality of gate electrodes (Fig. 3A: 485),
each of which includes an electrode portion (Fig. 3B: first conductive pattern 485a) and a pad portion (Fig. 3A 485b),
the pad portion being disposed on one area of the electrode portion (Fig. 3B: first conductive pattern 485a and pad 485b);
And a plurality of interlayer insulating layers (Fig. 3A: first insulation patterns 315) that are stacked alternately with the plurality of gate electrodes (Fig. 3A: first insulation patterns 315 between neighboring ones of the gate electrodes 485),
the stack having a connection area (Fig. 3A: region II) in which the pad portions of the plurality of gate electrodes are disposed in step shapes (Fig. 3A: pad portions 485b);
a row connection contact passing through the connection area and passing through a corresponding pad portion of a corresponding gate electrode (Fig. 3A: contact plugs 510),
among the plurality of gate electrodes, thereby connecting to the corresponding pad portion of the corresponding gate electrode (Paragraph 0010, lines 12-16);
and a plurality of first insulating patterns disposed between the row connection contact and side surfaces of electrode portions of gate electrodes that face the row connection contact (Fig. 3A: second insulation pattern 505, paragraph 0055, lines 10-13).
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Regarding claim 3; Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Further, Son teaches wherein each of the plurality of first insulating patterns (Fig 3B: insulation pattern 505) includes a first surface that faces the electrode portion (Fig 3B: 485a) and a second surface that faces the row connection contact (Fig 3B: contact plugs 510), and wherein the first surface is aligned with side surfaces of interlayer insulating layers that face the row connection contact (See Son: Annotated Fig. 3B shared in this OA, where the first surface and side surface are parallelly aligned).
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Regarding claim 4; Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Further, Son teaches wherein each of the plurality of first insulating patterns (Fig 3B: insulation pattern 505) includes a first surface that faces the electrode portion (Fig 3B: 485a) and a second surface that faces the row connection contact (Fig 3B: contact plugs 510), and wherein the second surface includes a curved surface (See Son: Annotated Fig. 1 shared in this OA).
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Regarding claim 6; Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Further, Son teaches the three-dimensional memory device comprising
a through contact passing through the stack (Fig. 3A: contact plug 510, See Son: Second Version of Annotated Fig. 3A shared in this OA);
and a plurality of second insulating patterns disposed on side surfaces of gate electrodes that face the through contact (Fig. 3A: insulation pattern 505)
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Regarding claim 7; Son teaches all the limitations of the three-dimensional memory device according to claim 6.
Further, Son teaches wherein the plurality of second insulating patterns (Fig. 3A: insulation pattern 505) are made of the same material as the plurality of first insulating patterns (Fig. 3A: insulation pattern 505).
Regarding claim 8; Son teaches all the limitations of the three-dimensional memory device according to claim 7.
Further, Son teaches wherein each of the plurality of second insulating patterns (Fig. 3B: insulation pattern 505) includes a first surface that faces the electrode portion (Fig. 3B: 485a) and a second surface that faces the through contact (Fig. 3B: contact plug 510), and wherein the first surface is aligned with side surfaces of interlayer insulating layers that face the through contact (See Son: Annotated Fig. 3B shared in this OA, where the first surface and side surface are parallelly aligned).
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Regarding claim 12; Son teaches a three-dimensional memory device (Fig. 3A: vertical memory device, paragraph 0004) comprising:
a first semiconductor structure including a peripheral circuit (See Son: Third Version of Annotated Fig. 3A shared in this OA).
and a second semiconductor structure disposed on the first semiconductor structure (See Son: Third Version of Annotated Fig. 3A shared in this OA), the second semiconductor structure comprising:
a source plate disposed on the first semiconductor structure (Fig. 3A: common source line (CSL) 520);
a stack disposed on the source plate (See Son: Third Version of Annotated Fig. 3A shared in this OA, described in paragraph 0025), the stack including:
a plurality of gate electrodes (Fig. 3A: 485),
each of which includes an electrode portion (Fig. 3B: conductive pattern 485a) and a pad portion (Fig. 3A: 485b)
the pad portion being disposed on one area of the electrode portion (Fig. 3B: first conductive pattern 485a and pad 485b);
and a plurality of interlayer insulating layers (Fig. 3A: first insulation patterns 315) that are stacked alternately with the plurality of gate electrodes (Fig. 3A: first insulation patterns 315 between neighboring ones of the gate electrodes 485),
the stack having a connection area (Fig. 3A: region II) in which the pad portions of the plurality of gate electrodes are disposed in step shapes (Fig. 3A: pad portions 485b);
a row connection contact passing through the connection area and passing through a corresponding pad portion of a corresponding gate electrode (Fig. 3A: contact plugs 510),
among the plurality of gate electrodes, thereby connecting to the corresponding pad portion of the corresponding gate electrode (Paragraph 0010, lines 12-16);
and a plurality of first insulating patterns disposed between the row connection contact and side surfaces of electrode portions of gate electrodes that face the row connection contact (Fig. 3A: second insulation pattern 505, paragraph 0055, lines 10-13).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al, US 20190326316 A1 (Son) in view of Kanamori et al, US 20230054445 A1 (Kanamori).
Regarding claim 2, Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Son does not teach wherein the plurality of first insulating patterns include SiOC.
However, Kanamori teaches the plurality of first insulating patterns include SiOC (Fig. 3A: insulating patterns 152, paragraph 0062).
Son and Kanamori are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son by having the plurality of first insulating patterns include SiOC as disclosed in Kanamori to increase the temperature resistance of the first insulating patterns.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al, US 20190326316 A1 (Son) in view of Choi, KR 20230163129 A (Choi).
Regarding claim 5, Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Son does not teach wherein the row connection contact is formed integrally with the one gate electrode.
However, Choi teaches wherein the row connection contact (Fig 7: tubular conductive pattern 185P1' of the conductive gate contact 185') is formed integrally with the one gate electrode (Fig. 7: conductive layer 111' with gate electrode pattern GE).
Son and Choi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son by having the row connection contact formed integrally with the one gate electrode as disclosed in Choi to improve the structural integrity, while at the same time allowing electrical connection.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al, US 20190326316 A1 (Son) in view of Lee, US 20210174839 A1 (Lee).
Regarding claim 9, as best understood based on the 35 U.S.C. 112(b) issue identified above, Son teaches all the limitations of the three-dimensional memory device according to claim 1.
Son does not teach a support passing through the stack; and a plurality of second insulating patterns (interpreted as a plurality of third insulting patterns) disposed on side surfaces of gate electrodes that face the support.
However, Lee teaches a support passing through the stack (Fig. 5C: vertical contact part VCP); and a plurality of third insulating patterns disposed on side surfaces of gate electrodes that face the support (Fig. 5C: spacer insulating layers 51s).
Son and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son by adding a support and a plurality of third insulating patterns disposed on side surfaces of gate electrodes that face the support as disclosed in Lee in order to prevent the stack from collapsing or bending.
Regarding claim 10, as best understood based on the 35 U.S.C. 112(b) issue identified above, Son in view of Lee teaches all the limitations of the three-dimensional memory device according to claim 9, wherein the plurality of second insulating patterns (interpreted as a plurality of third insulting patterns (Lee: Fig. 5E spacer insulating layers 51s)) are made of the same material as the plurality of first insulating patterns (Lee: Fig. 5C: 51s is used for first insulating patterns and third insulating patterns).
It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son by having a plurality of third insulating patterns be made of the same material as the plurality of first insulating patterns as disclosed by Lee so third insulating patterns can be formed in the same process of forming the first insulating patterns.
Regarding claim 11, as best understood based on the 35 U.S.C. 112(b) issue identified above, Son in view of Lee teaches all the limitations of the three-dimensional memory device according to claim 9, wherein each of the plurality of second insulating patterns (interpreted as a plurality of third insulting patterns (Lee: Fig. 5E spacer insulating layers 51s)) includes a first surface that faces the electrode portion (Lee: Fig. 5E: conductive pattern CP) and a second surface that faces the support (Lee: Fig. 5E: vertical contact part VCP), and wherein the first surface is aligned with side surfaces of interlayer insulating layers that face the support (Lee: See annotated Fig. 5E shared in this OA, first surface and side surfaces of interlayer insulating layers are parallelly aligned).
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It would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son to have a plurality of third insulating patterns with a first surface that faces the electrode portion and a second surface that faces the support, and wherein the first surface is aligned with side surfaces of interlayer insulating layers that face the support as disclosed in Lee in order to space the support apart from the conductive layers.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Son et al, US 20190326316 A1 (Son) in view of Lee, US 20220045093 A1 (Lee).
Regarding claim 13, Son teaches a three-dimensional memory device (Vertical memory device, paragraph 0004) comprising:
a first semiconductor structure (See Son: Third Version of Annotated Fig. 3A shared in this OA) having a peripheral circuit (Paragraph 0018, lines 14-17)
and a first bonding layer including a plurality of first bonding pads that are connected to the peripheral circuit;
and a second semiconductor structure bonded to the first semiconductor structure (See Son: Annotated Fig (3a) shared in this OA),
the second semiconductor structure comprising:
a second bonding layer including a plurality of second bonding pads that are bonded to the plurality of first bonding pads;
a stack disposed on the second bonding layer, the stack including:
a plurality of gate electrodes (Fig. 3A: 485),
each of which includes an electrode portion (Fig. 3B: conductive pattern 485a) and a pad portion (Fig. 3A: 485b),
the pad portion being disposed on one area of the electrode portion (Fig. 3B: first conductive pattern 485a and pad 485b);
And a plurality of interlayer insulating layers (Fig. 3A: first insulation patterns 315) that are stacked alternately with the plurality of gate electrodes (Fig. 3A: first insulation patterns 315 between neighboring ones of the gate electrodes 485),
the stack having a connection area (Fig. 3A: region II) in which the pad portions of the plurality of gate electrodes are disposed in step shapes (Fig. 3A: pad portions 485b);
a row connection contact passing through the connection area (Fig. 3A: contact plugs 510) and passing through a corresponding pad portion of a corresponding gate electrode (Fig. 3A: contact plug 510),
among the plurality of gate electrodes, thereby connecting to the corresponding pad portion of the corresponding gate electrode (Paragraph 0010, lines 12-16);
and a plurality of first insulating patterns disposed between the row connection contact and side surfaces of electrode portions of gate electrodes that face the row connection contact (Fig. 3A: second insulation pattern 505, Paragraph 0055, lines 10-13).
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Son does not teach a first semiconductor structure having a first bonding layer including a plurality of first bonding pads that are connected to the peripheral circuit, a second semiconductor structure comprising a second bonding layer including a plurality of second bonding pads that are bonded to the plurality of first bonding pads, or a stack disposed on the second bonding layer.
However, Lee teaches a first semiconductor structure having a first bonding layer (Fig 5: first bonding structure BDS1) including a plurality of first bonding pads that are connected to the peripheral circuit (Fig. 5: first bonding pads BP1), a second semiconductor structure comprising a second bonding layer (Fig. 5: second bonding structure BDS2) including a plurality of second bonding pads that are bonded to the plurality of first bonding pads (Fig. 5: second bonding pads BP2), or a stack disposed on the second bonding layer (Fig. 5: stack STA and second bonding layer BDS2).
Son and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Son by adding a first bonding layer including a plurality of first bonding pads that are connected to the peripheral circuit onto the first semiconductor structure, adding a second bonding layer including a plurality of second bonding pads that are bonded to the plurality of first bonding pads to the second semiconductor structure, and having a stack disposed on a second bonding layer as disclosed in Lee to allow the use of different substrates since the substrates will not be in direct contact with a bonding layer in between.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUBRIE I HETHERINGTON whose telephone number is (571)270-0666. The examiner can normally be reached M-Th 7:30-5, Fr 7:30-4.
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/AUBRIE IRENE HETHERINGTON/Examiner, Art Unit 2817 06/22/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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