DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement submitted on 11 Jun 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 13: the limitation "determine the one or more first properties of the first current path of the switching converter at a first time step; calculate the current flow through the energy storage element at a second time step using the determined one or more properties at the first time step; generate the digitized current signal comprising the digital representation of the current flow through the energy storage element at the second time step, as calculated.” There are no figures with time steps depicted.
Claim 16: the limitation “an off phase". Fig 2(d) only shows the magnetization and demagnetization phases.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 15 is objected to because of the following informalities:
Claim 15: "first step" should be replaced with "first time step".
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 15: the limitation “determine a first variable by multiplying the first current path resistance at the first time step and the current flow through the energy storage element at the first time step” is not clear or consistent with Claim 13, from which 15 depends. Claim 13 states, “calculate the current flow through the energy storage element at a second time step”. If the current flow through the energy storage element is not calculated until the second time step, it is unclear how a first variable could be calculated using a calculation that is not yet completed. For the purposes of examination, the examiner interprets the above phrase to mean multiplying the first current path resistance from the previous time step and the current flow through the energy storage element from the previous time step to determine a variable in the current time step.
Regarding Claim 15: the limitation “determine the current flow through the energy storage element at the second time step by adding the current flow through the energy storage element at the first [time] step” is not clear due to Claim 13 stating that the current calculation is not calculated until the second time step. For the purposes of examination, the examiner interprets the above phrase to mean multiplying the first current path resistance from the previous time step and the current flow through the energy storage element from the previous time step to determine a variable in the current time step.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8, 13-14, 16-18, & 23-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by D'Souza (US 12176808 B2).
Regarding Claim 1, D'Souza teaches a current synthesizer (350, Fig 3/4) for a switching converter (220-1, Fig 3) comprising an energy storage element (225A-1, Fig 3/4) and a first pass device (330, Fig 3/4), the switching converter configured to receive an input voltage (Vin/201, Fig 3) and to provide an output voltage (Va/240, Fig 3), the current synthesizer being configured to: determine one or more first properties ("the current (IL) through inductor 225A-1 is sensed by circuit 40 by measuring/obtaining the voltage across the LS switch 330", Col 8 [37-39]) of a first current path of the switching converter ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1", Col 6 [57-59]), the first current path comprising the first pass device and the energy storage element ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1", Col 6 [57-59]); calculate a current flow through the energy storage element using the determined one or more first properties ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude, inductor 225A-1", Col 7 [18-21]); and generate a digitized current signal ("CSA-1 can be a replica current, voltage and digital values", Col 6 [2-3]), the digitized current signal being a digital representation of the current flow through the energy storage element, as calculated ("CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values", Col 6 [1-3]).
Regarding Claim 2, D'Souza teaches all of the limitations of Claim 1 above, and further teaches a
Regarding Claim 4, D'Souza teaches all of the limitations of Claim 1 above, and further teaches wherein the first pass device is a first power switch or a first diode (330 is a power switch, Fig 3/4).
Regarding Claim 5, it is rejected for the same reasons as stated above for Claim 2.
Regarding Claim 8, D'Souza teaches all of the limitations of Claim 2 above, and further teaches wherein the first current path voltage comprises the output voltage ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1 and load", Col 6 [57-59]) and a first node voltage (" current emulator block 350 receives the voltage across LS MOSFET 330 via paths 335", Col 6 [37-39]).
Regarding Claim 13, D'Souza teaches all of the limitations of Claim 1 above, and further teaches determine the one or more first properties of the first current path of the switching converter at a first time step ("Circuit 40 measures (or senses, rather than estimating) the inductor current I L (inductor 225A-1 of FIG. 2 is also shown for clarity) in the second phases (i.e., when LS switch 330 (FIG. 3) is closed and driving the inductor current, HS switch 320 being open in the second phases)." e.g. at t52 of cycle 1 a voltage is measured at 521, and at t53 a voltage is measured corresponding to 522, Col 7 [53-55]); calculate the current flow through the energy storage element at a second time step using the determined one or more properties at the first time step ("Circuit 41 of current emulator block 350 operates to create a replica of inductor current in the first phases without sensing or measuring the inductor current in the first phases" and "In the next iteration, starting at the beginning of cycle2, comparator 465 compares the voltages at nodes 466 and 467, which would respectively correspond to points 522 and 521" where 521 and 522 are measured during cycle 1, Col 7 [61-62] & Col 11 [14-17); generate the digitized current signal comprising the digital representation of the current flow through the energy storage element at the second time step, as calculated ("CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values", Col 6 [1-3]).
Regarding Claim 14, it is rejected for the same reasons as stated above for Claim 2.
Regarding Claim 16, D'Souza teaches all of the limitations of Claim 1 above, and further teaches configured to generate the digitized current signal when the switching converter is in at least one of: a magnetization phase ("Circuit 41 operates to estimate and create a replica of inductor current in the first phases", where the first phases have a positive slope, Col 7 [61-62]); a demagnetization phase; and/or an off phase (Circuit 40 re-creates (i.e., creates a replica of) the inductor current in the second phases. As may be observed from FIG. 2B, the inductor current in the second phases has a falling (negative slope).", Col 7 [54-58]).
Regarding Claim 17, D'Souza teaches all of the limitations of Claim 1 above, and further teaches wherein the switching converter comprises a second power switch (320, Fig 3), the current synthesizer being configured to: determine the one or more first properties ("the current (IL) through inductor 225A-1 is sensed by circuit 40 by measuring/obtaining the voltage across the LS switch 330", Col 8 [37-39]) of the first current path of the switching converter ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1", Col 6 [57-59]) during a first phase ("Circuit 40 measures (or senses, rather than estimating) the inductor current I L (inductor 225A-1 of FIG. 2 is also shown for clarity) in the second phases (i.e., when LS switch 330 (FIG. 3) is closed and driving the inductor current, HS switch 320 being open in the second phases)." e.g. at t52 of cycle 1 a voltage is measured at 521, and at t53 a voltage is measured corresponding to 522, Col 7 [53-55]); calculate the current flow through the energy storage element using the determined one or more properties during the first phase ("Circuit 40 re-creates (i.e., creates a replica of) the inductor current in the second phases.", Col 7 [54-55]); generate a first portion of the digitized current signal during the first phase ("Current emulator block 350 provides the replica inductor current in the second phases at/on node/path CSA-1 (213)", Col 7 [58-60]), using the calculated current flow during the first phase ("CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values", Col 6 [1-3]); determine one or more second properties of a second current path of the switching converter during a second phase ("estimate and create a replica (scaled or otherwise) of the inductor current in the first phases.", Col 7 [27-29]), the second path comprising the second power switch and the energy storage element (second switch is 320 and inductor 225A-1, Fig 3); calculate the current flow through the energy storage element using the determined one or more second properties ("Circuit 41 of current emulator block 350 operates to create a replica of inductor current in the first phases", Col 9 [58-59]); and generate a second portion of the digitized current signal during the second phase (" Current emulator block 350 operates to generate replicas of the inductor current in the first phases", Col 7 [12-13]), using the calculated current flow during the second phase ("create a replica (scaled or otherwise) of the inductor current in the first phases.", Col 7 [27-29]) ("CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values", Col 6 [1-3]).
Regarding Claim 18, D'Souza teaches all of the limitations of Claim 1 above, and further teaches the switching converter comprises a controller (210, Fig 2A) configured to provide a second control signal (312, Fig 3) to the second power switch (320, Fig 2A); and the switching converter is operating in the first phase when the second power switch is in a first configuration ("When PWMA-1 is a logic low (corresponding to the second phase), gate driver 310 generates respective appropriate voltages on paths 312 and 313 to switch OFF MOSFET 320 and switch ON MOSFET 330.", Col 6 [49-53]) and operating in the second phase when the second power switch is in a second configuration ("PWMA-1 is a logic high (corresponding to the first phase), gate driver 310 generates respective appropriate voltages on paths 312 (en-HS) and 313 (en-LS) to switch ON MOSFET 320 and switch OFF MOSFET 330.", Col 6 [46-49]).
Regarding Claim 23, D'Souza teaches a power converter system (100, Fig 1) comprising: a current synthesizer (350, Fig 3/4); and a switching converter (220-1, Fig 3) comprising: an energy storage element (225A-1, Fig 3/4) and a first pass device (330, Fig 3/4), the switching converter configured to receive an input voltage (Vin/201, Fig 3) and to provide an output voltage (Va/240, Fig 3); wherein:the current synthesizer is configured to: determine one or more first properties ("the current (IL) through inductor 225A-1 is sensed by circuit 40 by measuring/obtaining the voltage across the LS switch 330 ", Col 8 [37-39]) of a first current path of the switching converter ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1", Col 6 [57-59]), the first current path comprising the first pass device and the energy storage element ("When PWMA-1 is logic low, the inductor current flows in the loop formed by LS MOSFET 330, inductor 225A-1", Col 6 [57-59]); calculate a current flow through the energy storage element using the determined one or more first properties ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude, inductor 225A-1", Col 7 [18-21]); and generate a digitized current signal ("CSA-1 can be a replica current, voltage and digital values", Col 6 [2-3]), the digitized current signal being a digital representation of the current flow through the energy storage element, as calculated ("CSA-1 213 represents the current flowing through inductor 225A-1. CSA-1 can be a replica current, voltage and digital values", Col 6 [1-3]).
Regarding Claim 24, it is rejected for the same reasons as stated above for Claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6-7, & 9 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza (US 12176808 B2), in view of Guthrie (US 9419627 B2).
Regarding Claim 3, D'Souza teaches all of the limitations of Claim 2 above.
D'Souza does not teach wherein the first current path resistance comprises an equivalent series resistance of the inductor and a first pass device resistance of the first pass device.
Guthrie teaches a conventional current synthesizer correction (see Fig 13) including wherein the first current path resistance comprises an equivalent series resistance of the inductor and a first pass device resistance of the first pass device ("FIG. 13 shows a conceptual model 1300 of a lossy circuit (based on the model shown in FIG. 11), indicating various resistances that may be accounted for, including the on resistance of the low-side FET (Ron.sub.EFF), the equivalent series resistance of the inductor (DCR)", Col 10 [5-9]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the conventional current synthesizer correction in D'Souza, as taught by Guthrie, as it provides the advantage of improving the accuracy of the current synthesizer for a more efficient converter (Col 15 [9-13] of Guthrie).
Regarding Claim 6, D'Souza teaches all of the limitations of Claim 5 above.
D'Souza does not teach wherein the first current path resistance comprises an equivalent series resistance of the inductor and a first power switch resistance of the first power switch.
Guthrie teaches a conventional current synthesizer correction (see Fig 13) including wherein the first current path resistance comprises an equivalent series resistance of the inductor and a first power switch resistance of the first power switch ("FIG. 13 shows a conceptual model 1300 of a lossy circuit (based on the model shown in FIG. 11), indicating various resistances that may be accounted for, including the on resistance of the low-side FET (Ron.sub.EFF), the equivalent series resistance of the inductor (DCR)", Col 10 [5-9]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the conventional current synthesizer that takes various resistances of components in the system into account in D'Souza, as taught by Guthrie, as it provides the advantage of improving the accuracy of the current synthesizer for a more efficient converter (Col 15 [9-13] of Guthrie).
Regarding Claim 7, the combination of D'Souza and Guthrie teaches all of the limitations of Claim 6 above, and further teaches wherein the first power switch resistance is an on resistance of the first power switch or a body diode resistance of the first power switch ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude", Col 7 [18-21]).
Regarding Claim 9, D'Souza teaches all of the limitations of Claim 8 above, and further teaches wherein the switching converter comprises a voltage detector configured to detect the first node voltage ("current emulator block 350 receives the voltage across LS MOSFET 330 via paths 335" where 335 is the voltage at the node between 320 and 330, Fig 3, Col 7 [16-17]).
D'Souza does not teach the switching converter comprises a voltage detector configured to detect the output voltage.
Guthrie teaches a conventional current synthesizer correction that comprises a voltage detector configured to detect the output voltage (Vout is sampled, Fig 7, Col 6 [46-48]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the conventional current synthesizer correction in D'Souza, as taught by Guthrie, as it provides the advantage of improving the accuracy of the current synthesizer for a more efficient converter (Col 15 [14-15] of Guthrie).
Claims 10-12, & 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza (US 12176808 B2), in view of Fosler (US 20060023476 A1).
Regarding Claim 10, D'Souza teaches all of the limitations of Claim 2, and further teaches comprising a memory storage element (memory Storage 130, Fig 1); wherein at least one of the first current path resistance and the inductance of the inductor ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude", Col 7 [18-21]).
D'Souza does not teach a lookup table for storing calibration data; are determined using at least a portion of the calibration data.
Fosler teaches a conventional memory (see [0159-160]) including a memory storage element comprising (memory, [0159]): lookup table (“look-up table that can be stored in the memory", [0159]) for storing calibration data (it is well known in the art that a lookup table can be used to determine an unknown value, like the current path resistance, by measuring a different circuit value and finding the corresponding value for the current path resistance in a lookup table, [0159]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the memory in D'Souza, as taught by Fosler, as it provides the advantage of providing faster calculations for a more power efficient operation ([0885] of Fosler).
Regarding Claim 11, the recitation of the “inductance of the inductor” is not required in Claim 10. Therefore, the additional limitation(s) required in Claim 11 is not applicable.
Regarding Claim 12, the combination of D'Souza and Fosler teaches all of the limitations of Claim 10, and further teaches determine the first current path resistance using one or both of a gate drive voltage and a temperature value ("Once the current is sensed, then the value of V.sub.REF output by the reference DAC 506 is then set. This is set in accordance with a look-up table that can be stored in the memory", a person skilled in the art could use a lookup table to use a gate drive voltage or a temperature value to lookup a value corresponding to a current path resistance, [0159] of Fosler).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza (US 12176808 B2), in view of de Cremoux (US 20230155472 A1).
Regarding Claim 19, D'Souza teaches all of the limitations of Claim 17 above, and further teaches wherein the one or more first properties of the first current path comprises: a first current path resistance ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude", Col 7 [18-21]); a first current path voltage ("the current (IL) through inductor 225A-1 is sensed by circuit 40 by measuring/obtaining the voltage across the LS switch 330 ", Col 8 [37-39]); and/or an inductance of the energy storage element, wherein the energy storage element comprises an inductor (225A-1 is an inductor, Fig 3/4).
D'Souza does not teach the one or more second properties of the second current path comprises: a second current path resistance; a second current path voltage; and/or the inductance of the energy storage element.
de Cremoux teaches a conventional current sensing circuit for use in a power converter (see Fig 13) including the one or more second properties of the second current path comprises: a second current path resistance ("IHS×RDSON=IOUT×RDSON×D" where IHS is the current through high side switch 1308 and RDSON is the internal resistance, Fig 13, [0254]); a second current path voltage; and/or the inductance of the energy storage element ("A voltage VDAC is then provided at the node 834. The compensating voltage VDAC is equal to a voltage difference between the first sensor terminal 831 and the second sensor terminal 833 of the sensor switch 708. If the sensor switch 708 is selected to have an internal resistance RDSON×k, as previously discussed, then: VDAC=RDSON×k×IDAC.", [0196]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the current sensing circuit in D'Souza, as taught by de Cremoux, as it provides the advantage very accurately measuring output or input current of a switching power converter ([0256] of de Cremoux).
Regarding Claim 20, the combination of D'Souza and de Cremoux teaches all of the limitations of Claim 19 above, and further teaches wherein: the first current path voltage comprises the output voltage and a first node voltage ("In the example of FIG. 3, current emulator block 350 receives the voltage across LS MOSFET 330 via paths 335 and 399 (ground) in the second phases.", where 335 is the first node voltage, Col 7 [16-17] of D'Souza); and/or the second current path voltage comprises the output voltage and a second node voltage ("PWMA-1 is logic high, current flows from Vin to the load (connected to Va node, but not shown) via HS MOSFET 320 and inductor 225A-1 with rising slope.", where Va is the output voltage node, Col 6 [54-59] of D'Souza).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over D'Souza (US 12176808 B2), in view of de Cremoux (US 20230155472 A1), and further in view of Fosler (US 20060023476 A1).
Regarding Claim 21, the combination of D'Souza and de Cremoux teaches all of the limitations of Claim 19, and further teaches comprising a memory storage element (memory Storage 130, Fig 1); wherein at least one of the first current path resistance and the inductance of the inductor ("Current emulator block 350 in effect divides the measured voltage with the ON-resistance of LS MOSFET 330 to obtain the inductor current magnitude", Col 7 [18-21]).
The combination of D'Souza and de Cremoux does not teach a lookup table for storing calibration data; are determined using at least a portion of the calibration data.
Fosler teaches a conventional memory (see [0159-160]) including a memory storage element comprising (memory, [0159]): lookup table (“look-up table that can be stored in the memory", [0159]) for storing calibration data (it is well known in the art that a lookup table can be used to determine an unknown value, like the current path resistance, by measuring a different circuit value and finding the corresponding value for the current path resistance in a lookup table, [0159]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the memory in D'Souza, as taught by Fosler, as it provides the advantage of providing faster calculations for a more power efficient operation ([0885] of Fosler).
Regarding Claim 22, the recitation of the “inductance of the inductor” is not required in Claim 21. Therefore, the additional limitation(s) required in Claim 22 is not applicable.
Allowable Subject Matter
Claim 15 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 15, D'Souza teaches all of the limitations of Claim 14.
D'Souza does not teach configured to calculate the current flow through the energy storage element at the second time step by: determine a first variable by multiplying the first current path resistance at the first time step and the current flow through the energy storage element at the first time step; determine a second variable by subtracting the first variable from the first current path voltage at the first time step; determine a third variable by multiplying the second variable with the time step difference between the second and first time steps, and dividing by the inductance; and determine the current flow through the energy storage element at the second time step by adding the current flow through the energy storage element at the first step to the third variable.
Prior art de Cremoux (US 20230155472 A1), Guthrie (US 9419627 B2), and Fosler (US 20060023476 A1) are considered to be the closest prior art.
de Cremoux teaches configured to calculate the current flow through the energy storage element at the second time step by: determine a first variable (VLS, [209]) by multiplying the first current path resistance ("low side switch has an internal resistance RSDON", [206-209]) at the first time step ("Over a period Δt, the low side switch 808 is opened and closed according to the duty cycle (1−D), hence IOUT=ILS/(1−D)", [210]) and the current flow through the energy storage element at the first time step ("The voltage drop VLS across the terminal of the low side switch 808 is equal or approximately equal to the current ILS flowing through the low side switch 808 multiplied by the internal resistance of the switch 808, that is: VLS=ILS×RDSON", [0209]).
However, none of the prior art, taken singly or in combination, teach “determine a second variable by subtracting the first variable from the first current path voltage at the first time step; determine a third variable by multiplying the second variable with the time step difference between the second and first time steps, and dividing by the inductance; and determine the current flow through the energy storage element at the second time step by adding the current flow through the energy storage element at the first [time] step to the third variable.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.C.C./Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838