Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed on 5/28/2024 which claims priority of provisional application 63/469136 filed on 5/26/2023. Claims 1-15 are pending in the case. Claims 1, 5, and 9 are independent claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yudanov (US 20220156564 A1).
Referring to claims 1 and 9, Yudanov discloses a hardware encoder configured for encoding external data into spikes for spiking neural networks, ([0018] of Yudanov, memory architecture for implementing a spiking neural network (SNN)) the hardware encoder comprising:
an input handler configured for managing input data using one or more registers and one or more counters; ([0026] of Yudanov, memory element such as registers… [0054] of Yudanov, incrementation functionality of memory can be achieved by counters)
a spike generator configured for generating a spike-train using a look-up table (LUT) and the input data; ([0035] of Yudanov, input filter including lookup table) and
a neuron selector configured for routing the spike-train from the spike generator to a selected neuron or cluster of neurons. ([0035] of Yudanov, input filter including lookup table comprises the neuron IDs of nodes and The input 112 and output 115 filters may be configured to perform matching operations to match the source neuron ID of an inbound spike message to the target synapse of a target neuron within the node 100, where the target neurons are linked to the source neuron via a synaptic connection.)
Referring to claims 2 and 10, Yudanov discloses the hardware encoder of claim 1, wherein the hardware encoder is configured for supported rate, temporal, and multi-spikes encoding. ([0053] of Yudanov, “To explain further, for a particular time step, a set of spikes passes through the input filter 112 and is stored in a spike group within the spike cache 413. The spike group may have an identifier (e.g., label “0”) indicating that it is the group of the most recent spikes. The labels for subsequent groups are incremented by 1. There may be as many spike groups as there are time steps in the maximum possible delay. For example, given the maximum delay of 100 milliseconds and time step 1 millisecond, there are 100 spike groups and associated labels. These spike groups make up the spike cache 413 with temporal locality and a schedule associated with processing spikes according to this locality. In some embodiments, spike messages do not need to remain stored for entire duration until they become associated with the largest delay bucket (e.g., 100 milliseconds). Rather, they can be removed (invalidated) from the cache as soon as their longest delay is processed. Thus, this helps to keep the cache utilization efficient.”)
Referring to claims 3 and 11, Yudanov discloses the hardware encoder of claim 1, wherein the hardware encoder is configured for supporting different sizes for an encoding frame. ([0068] of Yudanov, spiking can be done for different clock cycles, which is different sizes of an encoding frame/interval)
Referring to claims 4 and 12, Yudanov discloses the hardware encoder of claim 1, wherein the hardware encoder is reconfigurable at runtime by virtue of the LUT. ([0176] of Yudanov, “The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer.”)
Referring to claim 5, Yudanov discloses a communication system built using a hierarchical network-on-chip (NoC) architecture for globally sparse, locally dense communication systems, the communication system comprising: a circuit switching level; ([0170] of Yudanov, circuit switch or bridge) a bandwidth-focused topology; ([0037] of Yudanov, bandwidth requirement to allow for node interconnectivity) and a latency-focused topology. ([0114]-[0115] of Yudanov, latency operation of the delay)
Referring to claim 6, Yudanov discloses the communication system of claim 5, wherein the circuit switching level is implemented as a multistage network topology, the bandwidth-focused topology comprises a mesh network, ([0037] of Yudanov, The fabric 132 may need to achieve a minimum bandwidth to support all connected nodes 100. The bandwidth requirements to allow for node interconnectivity may be reduced using an intelligent allocation of neurons and synapse placement. Synapses may be placed by neighboring with their connections to each other entirely within a node 100. This may reduce outbound spike message traffic. Normally, biological neurons have more local connections than remote ones. Thus, neural net connectomes naturally support this allocation. The allocation also could have a reduction gradient in connectivity with neighboring nodes 100 as they become more distant. As a result, another technique is a selective broadcast or multicast where most of the spike traffic is localized within neighboring nodes 100 with descent in connectivity gradient for more remote nodes 100. Additional filters (e.g., input filters 112 or output filters 115) can be placed along the fabric 132 to support selective broadcast, such that the filters can permit spike messages with certain neuron IDs into respective sections of the fabric 132. This can reduce redundant traffic”) and the latency-focused topology comprises a tree network. ([0036] of Yudanov, “A real neuron may have a delay that depends on the length of its axonal tree trunk common to all axonal branches, and specific from that common point to the synapse. In some embodiments of the SNN architecture, a spike message may include descriptors such as, for example, a neuron ID, time, a delay, and potentially a spike strength.”)
Referring to claim 7, Yudanov discloses the communication system of claim 6, wherein the communication system is configured for establishing communication of spikes in a spiking neural network and the circuit switching level is configured for supporting communication between neurons/nodes in the spiking neural network. ([0037] of Yudanov, The fabric 132 may need to achieve a minimum bandwidth to support all connected nodes 100. The bandwidth requirements to allow for node interconnectivity may be reduced using an intelligent allocation of neurons and synapse placement. Synapses may be placed by neighboring with their connections to each other entirely within a node 100. This may reduce outbound spike message traffic. Normally, biological neurons have more local connections than remote ones. Thus, neural net connectomes naturally support this allocation. The allocation also could have a reduction gradient in connectivity with neighboring nodes 100 as they become more distant. As a result, another technique is a selective broadcast or multicast where most of the spike traffic is localized within neighboring nodes 100 with descent in connectivity gradient for more remote nodes 100. Additional filters (e.g., input filters 112 or output filters 115) can be placed along the fabric 132 to support selective broadcast, such that the filters can permit spike messages with certain neuron IDs into respective sections of the fabric 132. This can reduce redundant traffic”)
Referring to claim 8, Yudanov discloses the communication system of claim 7, wherein the circuit switching level is configured for communicating using packetized address event representation. ([0132] of Yudanov, “spike messages may be generated according to a memory protocol (e.g., DDR) and then packetized into network packets according to a network protocol (e.g., Ethernet). This may involve encapsulating the spike message into a packet by adding preambles, headers, and other fields to the spike message.”)
Referring to claim 13, Yudanov discloses the method of claim 9, comprising communicating using communication system built using a hierarchical network-on-chip (NoC) architecture for globally sparse, locally dense communication systems, the communication system comprising a circuit switching level, ([0170] of Yudanov, circuit switch or bridge) a bandwidth-focused topology; ([0037] of Yudanov, bandwidth requirement to allow for node interconnectivity) and a latency-focused topology. ([0114]-[0115] of Yudanov, latency operation of the delay)
Referring to claim 14, Yudanov discloses the method of claim 9, wherein the circuit switching level is implemented as a multistage network topology, the bandwidth-focused topology comprises a mesh network, ([0037] of Yudanov, The fabric 132 may need to achieve a minimum bandwidth to support all connected nodes 100. The bandwidth requirements to allow for node interconnectivity may be reduced using an intelligent allocation of neurons and synapse placement. Synapses may be placed by neighboring with their connections to each other entirely within a node 100. This may reduce outbound spike message traffic. Normally, biological neurons have more local connections than remote ones. Thus, neural net connectomes naturally support this allocation. The allocation also could have a reduction gradient in connectivity with neighboring nodes 100 as they become more distant. As a result, another technique is a selective broadcast or multicast where most of the spike traffic is localized within neighboring nodes 100 with descent in connectivity gradient for more remote nodes 100. Additional filters (e.g., input filters 112 or output filters 115) can be placed along the fabric 132 to support selective broadcast, such that the filters can permit spike messages with certain neuron IDs into respective sections of the fabric 132. This can reduce redundant traffic”) and the latency-focused topology comprises a tree network. ([0036] of Yudanov, “A real neuron may have a delay that depends on the length of its axonal tree trunk common to all axonal branches, and specific from that common point to the synapse. In some embodiments of the SNN architecture, a spike message may include descriptors such as, for example, a neuron ID, time, a delay, and potentially a spike strength.”)
Referring to claim 15, Yudanov discloses the method of claim 14, wherein the communication system is configured for establishing communication of spikes in a spiking neural network and the circuit switching level is configured for supporting communication between neurons/nodes in the spiking neural network. ([0037] of Yudanov, The fabric 132 may need to achieve a minimum bandwidth to support all connected nodes 100. The bandwidth requirements to allow for node interconnectivity may be reduced using an intelligent allocation of neurons and synapse placement. Synapses may be placed by neighboring with their connections to each other entirely within a node 100. This may reduce outbound spike message traffic. Normally, biological neurons have more local connections than remote ones. Thus, neural net connectomes naturally support this allocation. The allocation also could have a reduction gradient in connectivity with neighboring nodes 100 as they become more distant. As a result, another technique is a selective broadcast or multicast where most of the spike traffic is localized within neighboring nodes 100 with descent in connectivity gradient for more remote nodes 100. Additional filters (e.g., input filters 112 or output filters 115) can be placed along the fabric 132 to support selective broadcast, such that the filters can permit spike messages with certain neuron IDs into respective sections of the fabric 132. This can reduce redundant traffic”)
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
“Low-Power Neuromorphic Hardware for Signal Processing Applications”, Rajendran et al, 2019, Machine learning has emerged as the dominant tool for implementing complex cognitive tasks that require supervised, unsupervised, and reinforcement learning. While the resulting machines have demonstrated in some cases even superhuman performance, their energy consumption has often proved to be prohibitive in the absence of costly supercomputers. Most state-of-the-art machine-learning solutions are based on memoryless models of neurons. This is unlike the neurons in the human brain that encode and process information using temporal information in spike events. The different computing principles underlying biological neurons and how they combine together to efficiently process information is believed to be a key factor behind their superior efficiency compared to current machine-learning systems.
Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
In the interests of compact prosecution, Applicant is invited to contact the examiner via electronic media pursuant to USPTO policy outlined MPEP § 502.03. All electronic communication must be authorized in writing. Applicant may wish to file an Internet Communications Authorization Form PTO/SB/439. Applicant may wish to request an interview using the Interview Practice website: http://;www.uspto.gov/patent/laws-and-regulations/interview-practice.
Applicant is reminded Internet e-mail may not be used for communication for matters under 35 U.S.C. § 132 or which otherwise require a signature. A reply to an Office action may NOT be communicated by Applicant to the USPTO via Internet e- mail. If such a reply is submitted by Applicant via Internet e-mail, a paper copy will be placed in the appropriate patent application file with an indication that the reply is NOT ENTERED. See MPEP § 502.03(II).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAIMEI JIANG whose telephone number is (571)270-1590. The examiner can normally be reached M-F 9-5pm.
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/HAIMEI JIANG/Primary Examiner, Art Unit 2142
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