Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 05/28/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/28/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2, 3, 17, 18, and 20 are objected to because of the following informalities: Regarding claim 2, in line 4, “voltage of the bias node” appears that it should read as “the voltage of the bias node”. Regarding claim 3, in line 8, “the control terminal” appears that it should read as “a control terminal”. Regarding claim 17, in line 1, “The bias acceleration system of claim 11” appears that it should read as “The method of claim 11”. Regarding claim 18, in line 1, “The method claim 11” appears that it should read as “The method of claim 11”. Regarding claim 20, in line 1-2, “a coupling control terminal” appears that it should read as “coupling a control terminal”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Svorc (US Patent Application Publication US 2016/0147246 A1) in view of Hummerston et al. (US Patent Application Publication US 2012/0007660 A1, hereinafter “Hummerston”). Regarding claim 1, Svorc discloses (see Fig. 4) a bias acceleration system (the fast start-up circuit of FIG. 4) for a reference bias generator (the current mirror circuit of FIG. 4 comprising current mirror circuit 40 and the main current mirror circuit comprising N1, N2, see [0026] "The circuitry of the second embodiment is basically the same as shown in FIG. 3 with the exception of the detail implementation of the amplifier A2 and the comparator circuitry 43"), the reference bias generator comprising a plurality of mirrored transistor devices (N2 and the plurality of output driver transistors inherent in the main current mirror circuit of FIG. 4, which per [0026] is the same as FIG. 3 where [0026] discloses "N3 to Nx are current mirror driver circuits to provide load current, Ibias_1 to Ibias_X") coupled in a mirrored configuration with a primary bias transistor device (N1 of FIG. 4, the input driver of the main current mirror circuit, see [0026] "main current mirror circuit comprising N1") at a bias node (nbias2 42 of FIG. 4, which is the node connecting the gates of the plurality of output driver transistors and filter capacitor C1, see [0027] "nbias2 to which is connected the gate capacitance of a plurality of transistor gates and a filter capacitor C1"), wherein the primary bias transistor device (N1) has a current path coupled to a bias current source (P2 of FIG. 4, being part of current mirror circuit 40, see [0026] "transistor P2 forms a part of a current mirror circuit 40 that provides input source current to the main current mirror circuit") activated by a reference enable signal (the enable/disable signal controlling switches S1 and S2 of FIG. 4, see [0027]–[0028] "When the circuit of FIG. 4 is first started up, switch S1 is opened"), the bias acceleration system comprising: a bias accelerator (amplifier A2 of FIG. 4, comprising transistors NA1 and NA2, see [0026] "The amplifier A2 comprises transistors NA1 and NA2") configured to apply current to the bias node (nbias2 42) in response to the bias current source (P2) when activated by the reference enable signal (see [0027] "The low source impedance of the output transistor NA2 of amplifier A2 is used to drive the high capacitance of the second part of the current mirror network nbias2"); and an activation controller (comparator circuitry 43, control signal SW, and switches S1, S2, S3 of FIG. 4, see [0028]) configured to enable the bias accelerator (amplifier A2) in response to the reference enable signal (see [0027] "When the circuit of FIG. 4 is first started up, switch S1 is opened" — S2 closed to connect amplifier A2) and to disable the bias accelerator when the bias current source stabilizes (see [0028] "When the current from N2 equals the current from P3 at the input node cc of the current comparator, control signal SW turns off switch S3 which latches the output of the comparator...the amplifier is disabled by the opening of S2 and S1 is closed to reconnect nbias to nbias2"). Svorc does not explicitly disclose wherein the bias accelerator is configured to amplify bias current applied to the primary bias transistor device and apply amplified current to the bias node (Examiner’s Note: The Amplifier A2 pf Svorc drives the bias node voltage using low output impedance (voltage-mode driving), but does not explicitly characterize this as amplifying the bias current itself). However, Hummerston teaches (see Fig. 4 and Fig. 5) a buffer amplifier (buffer 50 of FIG. 4) placed between a first limb (reference transistor 20 of FIG. 4) and at least one second limb (slave transistors 30 of FIG. 4) of a current mirror, wherein the buffer (50) has a low output impedance (R_out of FIG. 5, see [0038]) that effectively amplifies the current drive capability applied to the gate node of slave transistors 30 (the "bias node"), providing amplified current to charge the load capacitance (C_load of FIG. 5, see [0041] "the parasitic gate capacitances of the slave transistors in the second limbs 12, 14 and 18 have been identified as a load capacitor C_load"). Hummerston explicitly characterizes this as providing enhanced current to the bias node (see [0035] - [0040] "the buffer output impedance significantly less than the output impedance" resulting in a dramatically reduced time constant for charging C_load). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the bias acceleration system of Svorc wherein the bias accelerator is configured to amplify bias current applied to the primary bias transistor device and apply amplified current to the bias node, as taught by Hummerston, because providing a buffer between the reference limb and slave limbs of a current mirror provides enhanced current drive that helps reduce settling time.
Regarding claim 2, Svorc discloses (see Fig. 4) wherein the bias accelerator (amplifier A2) comprises an amplifier (A2 of FIG. 4) configured to drive a voltage of the bias node (voltage of nbias2 42 of FIG. 4) to a voltage level of an intermediate node (voltage of nbias 41 of FIG. 4, which is the node coupled between the primary bias transistor device N1 and the bias current source P2, see [0026] "The amplifier A2 is connected to the first part of the main current mirror network nbias through a connection to P2") coupled between the primary bias transistor device (N1) and the bias current source (P2) to accelerate stabilization of voltage of the bias node (see [0027] "the amplifier A2 detects the bring-up voltage of the first part of the current mirror network and controls the second part of the current mirror network to quickly follow the bring-up voltage of the first part"; see also [0018], which applies equally to the second embodiment per [0026] "The amplifier keeps the gate voltage of the rest of the current mirror at the same potential as the input transistor but since the output impedance of the amplifier is much lower than the output impedance of the current bias the net nbias2 follows net nbias").
Regarding claim 11, Svorc discloses (see Fig. 4) a method of accelerating activation (the fast start-up circuit of FIG. 4) and settling of a reference bias generator (the current mirror circuit of FIG. 4 comprising current mirror circuit 40 and the main current mirror circuit comprising N1, N2, see [0026] "The circuitry of the second embodiment is basically the same as shown in FIG. 3 with the exception of the detail implementation of the amplifier A2 and the comparator circuitry 43"), the reference bias generator comprising a plurality of mirrored transistor devices (N2 and the plurality of output driver transistors inherent in the main current mirror circuit of FIG. 4, which per [0026] is the same as FIG. 3 where [0021] discloses "N3 to Nx are current mirror driver circuits to provide load current, Ibias_1 to Ibias_X") coupled in a mirrored configuration with a primary bias transistor device (N1 of FIG. 4, the input driver of the main current mirror circuit, see [0026] "main current mirror circuit comprising N1") at a bias node (nbias2 42 of FIG. 4, which is the node connecting the gates of the plurality of output driver transistors and filter capacitor C1, see [0027] "nbias2 to which is connected the gate capacitance of a plurality of transistor gates and a filter capacitor C1"), wherein the primary bias transistor device (N1) has a current path coupled to a bias current source (P2 of FIG. 4, being part of current mirror circuit 40, see [0026] "transistor P2 forms a part of a current mirror circuit 40 that provides input source current to the main current mirror circuit") at an intermediate node (nbias 41 of FIG. 4, which is the node coupled between the primary bias transistor device N1 and the bias current source P2, see [0026] "The amplifier A2 is connected to the first part of the main current mirror network nbias through a connection to P2"), the method comprising: activating the bias current source to apply bias current to the primary bias transistor device (see [0027] "The low source impedance of the output transistor NA2 of amplifier A2 is used to drive the high capacitance of the second part of the current mirror network nbias2"); and removing the amplified current from the bias node when the bias current source stabilizes (see [0028] "When the current from N2 equals the current from P3 at the input node cc of the current comparator, control signal SW turns off switch S3 which latches the output of the comparator...the amplifier is disabled by the opening of S2 and S1 is closed to reconnect nbias to nbias2").
Svorc does not explicitly disclose amplifying the bias current applied to the primary bias transistor device to provide amplified current; and applying the amplified current to the bias node (Examiner’s Note: The Amplifier A2 pf Svorc drives the bias node voltage using low output impedance (voltage-mode driving), but does not explicitly characterize this as amplifying the bias current itself). However, Hummerston teaches (see Fig. 4 and Fig. 5) a buffer amplifier (buffer 50 of FIG. 4) placed between a first limb (reference transistor 20 of FIG. 4) and at least one second limb (slave transistors 30 of FIG. 4) of a current mirror, wherein the buffer (50) has a low output impedance (R_out of FIG. 5, see [0038]) that effectively amplifies the current drive capability applied to the gate node of slave transistors 30 (the "bias node"), providing amplified current to charge the load capacitance (C_load of FIG. 5, see [0041] "the parasitic gate capacitances of the slave transistors in the second limbs 12, 14 and 18 have been identified as a load capacitor C_load"). Hummerston explicitly characterizes this as providing enhanced current to the bias node (see [0035] - [0040] "the buffer output impedance significantly less than the output impedance" resulting in a dramatically reduced time constant for charging C_load). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Svorc to include amplifying the bias current applied to the primary bias transistor device to provide amplified current; and applying the amplified current to the bias node, as taught by Hummerston, because providing a buffer between the reference limb and slave limbs of a current mirror provides enhanced current drive that helps reduce settling time.
Regarding claim 12, Svorc discloses (see Fig. 4) driving a voltage of the bias node (voltage of nbias2 42 of FIG. 4) to a voltage level of the intermediate node (voltage of nbias 41 of FIG. 4) coupled between the primary bias transistor device and the bias current source to accelerate stabilization of voltage of the bias node (nbias 41 of FIG. 4, which is the node coupled between the primary bias transistor device N1 and the bias current source P2, see [0026] "The amplifier A2 is connected to the first part of the main current mirror network nbias through a connection to P2") coupled between the primary bias transistor device (N1) and the bias current source (P2) to accelerate stabilization of voltage of the bias node (see [0027] "the amplifier A2 detects the bring-up voltage of the first part of the current mirror network and controls the second part of the current mirror network to quickly follow the bring-up voltage of the first part"; see also [0018], which applies equally to the second embodiment per [0026] "The amplifier keeps the gate voltage of the rest of the current mirror at the same potential as the input transistor but since the output impedance of the amplifier is much lower than the output impedance of the current bias the net nbias2 follows net nbias").
Claims 6, 7, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Svorc in view of Hummerston, and further in view of Baranauskas et al. (US 2007/0241738 A1, hereinafter “Baranauskas”). Regarding claim 6, Svorc discloses (see Fig. 4) wherein the activation controller comprises: an auxiliary transistor device (N2 of FIG. 4, see [0028] "Transistor N2 provides a current from the second part of the current mirror network as the amplifier A2 powers up the second part of the network") coupled in a mirrored configuration with the primary bias transistor device (N1 — both N1 and N2 have their gates connected to nbias2 42 in the current mirror configuration); and a switch controller (control signal SW and associated logic of FIG. 4) that controls at least one switch (S1, S2, S3) to disconnect the bias accelerator (amplifier A2) from the reference bias generator in response to the comparator circuitry (43) detecting stabilization (see [0028] "control signal SW turns off switch S3 which latches the output of the comparator...the amplifier is disabled by the opening of S2 and S1 is closed to reconnect nbias to nbias2"). Svorc does not disclose a timer coupled to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the reference enable signal, where the switch controller disconnects the bias accelerator in response to timeout of the timer. However, Baranauskas teaches (see Fig. 6) a timer (comprising C1) coupled to the auxiliary transistor device (M1) that is initiated by current (icrg) received by the auxiliary transistor device in response to the reference enable signal (ON), where the switch controller (comprising circuit generating signal ON and NEN) disconnects the bias accelerator in response to timeout of the timer (see [0045] “Once capacitors C1 and C2 have achieved complete charge, the current flow through those capacitors goes to zero. This effectively places M4, ic2, M5, and M6, in a "zero" or negligible current state. The charge on capacitor C1 provides bias voltages and stability to the remaining current sources Iref1 to Irefn”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the bias acceleration system of Svorc to include a timer coupled to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the reference enable signal, where the switch controller disconnects the bias accelerator in response to timeout of the timer, as taught by Baranauskas, because it can help limit the time required for acceleration, which can help hasten stability. Regarding claim 7, Svorc discloses (see Fig. 4) wherein the switch controller is configured to control the at least one switch to disable the bias accelerator when the reference enable signal indicates a standby mode (in the disabled/standby state of FIG. 4: the disable switches are in their disabled positions and amplifier A2 is disconnected; per [0026] the second embodiment includes the same enable/disable switches as FIG. 3, see [0025] "The purpose of these switches is to disable, or enable, the current mirror circuitry"), to enable the bias accelerator when the reference enable signal indicates activation (upon enable: S1 opens, S2 closes, amplifier A2 is connected to drive nbias2, see [0027]), and to disable the bias accelerator upon timeout (equivalent to the time when comparator 43 triggers SW, wherein upon timeout, S1 closes reconnecting nbias/nbias2 and S2 opens disconnecting A2). Svorc does not disclose a timer. However, Baranauskas teaches (see Fig. 6) a timer (comprising C1; see [0045] “Once capacitors C1 and C2 have achieved complete charge, the current flow through those capacitors goes to zero. This effectively places M4, ic2, M5, and M6, in a "zero" or negligible current state. The charge on capacitor C1 provides bias voltages and stability to the remaining current sources Iref1 to Irefn”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the bias acceleration system of Svorc to include a timer, as taught by Baranauskas, because it can help limit the time required for acceleration, which can help hasten stability. Regarding claim 15, Svorc discloses (see Fig. 4) further comprising: in response to the activating of the bias current source: controlling at least one switch (S2) to couple a bias accelerator (amplifier A2) to the reference bias generator (S2 is turned on with activation of the current source P2); and controlling the at least one switch to disconnect the bias accelerator from the reference bias generator (see [0028] "control signal SW turns off switch S3 which latches the output of the comparator...the amplifier is disabled by the opening of S2 and S1 is closed to reconnect nbias to nbias2"). Svorc does not disclose initiating a timer; and controlling the at least one switch to disconnect the bias accelerator from the reference bias generator upon timeout of the timer. However, Baranauskas teaches (see Fig. 6) initiating a timer (comprising C1, initiated by ON); and controlling the at least one switch (M4) to disconnect the bias accelerator from the reference bias generator upon timeout of the timer (see [0045] “Once capacitors C1 and C2 have achieved complete charge, the current flow through those capacitors goes to zero. This effectively places M4, ic2, M5, and M6, in a "zero" or negligible current state. The charge on capacitor C1 provides bias voltages and stability to the remaining current sources Iref1 to Irefn”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Svorc to include initiating a timer; and controlling the at least one switch to disconnect the bias accelerator from the reference bias generator upon timeout of the timer, as taught by Baranauskas, because it can help limit the time required for acceleration, which can help hasten stability. Regarding claim 16, Svorc discloses (see Fig. 4) further comprising controlling the at least one switch (S2) to disable the bias accelerator when a reference enable signal (enable/disable) indicates a standby mode (in the disabled/standby state of FIG. 4: the disable switches are in their disabled positions and amplifier A2 is disconnected; per [0026] the second embodiment includes the same enable/disable switches as FIG. 3, see [0025] "The purpose of these switches is to disable, or enable, the current mirror circuitry"), to enable the bias accelerator when the reference enable signal indicates activation (upon enable: S1 opens, S2 closes, amplifier A2 is connected to drive nbias2, see [0027]), and to disable the bias accelerator upon timeout (equivalent to the time when comparator 43 triggers SW, wherein upon timeout, S1 closes reconnecting nbias/nbias2 and S2 opens disconnecting A2). Svorc does not disclose a timer. However, Baranauskas teaches (see Fig. 6) a timer (comprising C1; see [0045] “Once capacitors C1 and C2 have achieved complete charge, the current flow through those capacitors goes to zero. This effectively places M4, ic2, M5, and M6, in a "zero" or negligible current state. The charge on capacitor C1 provides bias voltages and stability to the remaining current sources Iref1 to Irefn”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Svorc to include a timer, as taught by Baranauskas, because it can help limit the time required for acceleration, which can help hasten stability. Regarding claim 17, Svorc discloses (see Fig. 4) further comprising: providing an auxiliary transistor device (N2 of FIG. 4, see [0028] "Transistor N2 provides a current from the second part of the current mirror network as the amplifier A2 powers up the second part of the network") coupled in a mirrored configuration with the primary bias transistor device (N1 — both N1 and N2 have their gates connected to nbias2 42 in the current mirror configuration); and controlling (via control signal SW and associated logic of FIG. 4) at least one switch (S1, S2, S3) for removing the amplified current from the bias node in response to the comparator circuitry (43) detecting stabilization (see [0028] "control signal SW turns off switch S3 which latches the output of the comparator...the amplifier is disabled by the opening of S2 and S1 is closed to reconnect nbias to nbias2". Svorce does not disclose coupling a timer to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the activating of the bias current source, and controlling at least one switch for removing the amplified current from the bias node in response to timeout of the timer. However, Baranauskas teaches (see Fig. 6) coupling a timer (comprising C1) to the auxiliary transistor device (M1) that is initiated by current (icrg) received by the auxiliary transistor device in response to the activating of the bias current source (ON), and controlling at least one switch (M4) for removing the amplified current from the bias node in response to timeout of the timer (see [0045] “Once capacitors C1 and C2 have achieved complete charge, the current flow through those capacitors goes to zero. This effectively places M4, ic2, M5, and M6, in a "zero" or negligible current state. The charge on capacitor C1 provides bias voltages and stability to the remaining current sources Iref1 to Irefn”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Svorc to include coupling a timer to the auxiliary transistor device that is initiated by current received by the auxiliary transistor device in response to the activating of the bias current source, and controlling at least one switch for removing the amplified current from the bias node in response to timeout of the timer, as taught by Baranauskas, because it can help limit the time required for acceleration, which can help hasten stability.
Allowable Subject Matter
Claims 3-5, 8-10, 13, 14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 3, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the bias accelerator comprises: a first transistor device having a current path coupled to the primary bias transistor device at an intermediate node and coupled between the primary bias transistor device and the bias current source; a second transistor device coupled in a mirrored configuration with the first transistor device; and a third transistor device coupled to the second transistor device and the bias node formed at the control terminal of the primary bias transistor device; wherein the first, second, and third transistor devices are configured to drive a voltage of the bias node to a voltage of the intermediate node upon activation of the bias current source.”. Claims 4-5 are objected due to their dependency on claim 3. Regarding Claim 8, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the bias acceleration system further comprises: a charge injection compensator that compensates for charge injection caused by the corresponding one of the plurality of mirrored transistor devices when turning the switch on or off.”. Regarding Claim 9, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the bias acceleration system further comprises: a capacitive device coupled between the bias node and a control terminal of the switch; and a buffer having an input receiving an activation signal for turning on and off the switch and having an output coupled to the control terminal of the switch.”.
Claim 10 is objected due to its dependency on claim 9. Regarding Claim 13, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “sensing the bias current applied to the primary bias transistor device; and wherein the amplifying and applying comprises: mirroring and amplifying the bias current and providing the amplified current to the bias node; and driving a voltage of the bias node to a voltage of the intermediate node.”. Claim 14 is objected due to its dependency on claim 13. Regarding Claim 18, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the method further comprises compensating for charge injection caused by the corresponding one of the plurality of mirrored transistor devices when turning the switch on or off.”. Regarding Claim 19, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the reference bias generator includes a switch configured to enable or disable a bias current output of a corresponding one of the plurality of mirrored transistor devices, wherein the method further comprises: coupling a capacitive device between the bias node and a control terminal of the switch; and coupling a buffer between an activation signal and the control terminal of the switch for turning on and off the switch.”. Claim 20 is objected due to its dependency on claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication 2008/0164948 A1 discloses a biasing current to speed up current mirror settling time. US Patent 9,312,747 B1 discloses a fast start-up circuit for low power current mirror. US Patent 7,852,168 B1 discloses a power efficient biasing circuit.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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