DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s response (Applicant’s remarks pages 5-10) correctly observes that the prior art considered in the most recent Office action (US 20210091092 (Noda) in view of US 20220093629 A1 (Kim et al), US 20200027835 A1 (Hsu), US 20200127006 A1 (Otsu et al), and US 20210265385 A1 (Rajashekhar et al)) does not teach or obviously suggest the limitation introduced in the amendment “wherein the gate contact plugs and the void-free pillar-type supporters are alternately arranged along the same axis extending in a first direction”. However, after further search and consideration it was found that US 20200027896 A1 (Eom) renders the new limitation obvious to a person of ordinary skill in the art (see Rejections under 35 USC 103 below for further details).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5-6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20210091092 (Noda) in view of US 20220093629 A1 (Kim et al hereinafter Kim), US 20200027835 A1 (Hsu), US 20200127006 A1 (Otsu et al hereinafter Otsu), and US 20200027896 A1 (Eom).
Regarding claim 1, Noda discloses a semiconductor device (FIGS. 1-3, semiconductor device 10 ¶ [0008-0010, 0019]]), comprising: a lower structure (FIGS. 2-3, peripheral circuit formation portion CUA ¶ [0028-0031]) including an interconnection (see annotated FIG. 2 below, interconnection below leftmost contact C3 in peripheral circuit formation portion CUA); a source contact structure (FIGS. 2-3, conductive layer SC located above portion CUA ¶ [0032-0033]) over the lower structure; a first contact plug that is coupled to the interconnection (annotated FIG. 2, “first contact plug” is coupled to the interconnection); a first alternating stack positioned over the first contact plug (FIGS. 2-3, layers SO and SN in oxide based region OXB ¶ [0019-0020]) and including first dielectric layers (FIGS. 2-3, layers SO in OXB ¶ [0048]) and gate-level dielectric layers (FIGS. 2-3, layers SN in OXB ¶ [0048]) that are alternately stacked (FIGS. 2-3, layers SO and SN are alternately stacked); a second alternating stack (FIGS. 2-3, layers SO stacked with word lines WL ¶ [0024]) positioned adjacent to the first alternating stack (FIGS. 2-3, the first stack in OXB is adjacent to the second stack outside OXB) and including second dielectric layers (FIGS. 2-3, insulating layers SO outside OXB ¶ [0033]) and gate electrodes (FIGS. 2-3 word lines WL ¶ [0033]) that are alternately stacked (FIGS. 2-3, layers SO and word lines WL are alternately stacked);
void-free line-type supporters (FIGS. 1 and 3, second slits ST2 ¶ [0074]) between the first alternating stack and the second alternating stack (FIG. 3, second slits ST2 are between the first and second alternating stacks); a second contact plug (FIG. 2, leftmost contact C3 ¶ [0025]) coupled to the first contact plug and penetrating the first alternating stack between the void-free line-type supporters (FIG. 1 and annotated FIG. 2, “second contact plug” is coupled to “first contact plug” and penetrates the first alternating stack); and gate contact plugs (FIG. 2, contacts CC ¶ [0037]) coupled to edges of the gate electrodes of the second alternating stack (FIG. 2, contacts CC are coupled to the word lines WL) and pillar-type supporters (FIGS. 1-3, columnar portions HR ¶ [0052-0057]) formed between the gate contact plugs (FIG. 2, pillars HR are formed between the two clusters of gate contact plugs CC at each side of the device).
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Noda does not teach that the first contact plug penetrates the source contact structure (the first contact plug is located below the source contact structure SC) or a conformal sidewall liner surrounding a sidewall of the second contact plug, does not explicitly teach that the pillar-type supporters are also void-free, and the pillar-type supporters penetrating a stepped structure of ends of the gate electrodes, wherein the gate contact plugs and the void-free pillar-type supporters are alternately arranged along the same axis extending in a first direction.
Regarding the limitation that “the first contact plug penetrates the source contact structure”, Kim discloses a semiconductor device (the device of FIG. 7 ¶ [0014]), comprising a lower structure (FIG. 7 peripheral circuit structure PS ¶ [0056-0057]) including an interconnection (FIG. 7, unlabeled nterconnection directly below LP1); a source contact structure (FIG. 7, source conductive pattern SC ¶ [0064]) over the lower structure; a first contact plug (FIG. 7, first pad pattern LP1 ¶ [0082-0083]) that is coupled to the interconnection and penetrates the source contact structure; and a second contact plug (FIG. 7, penetration plug TP1 ¶ [0062]) coupled to the first contact plug. A person or ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Noda in view of Kim such that the first contact plug penetrates the source contact structure by means of a simple substitution of the interconnection structure of Kim in place of that of Noda, since both interconnection structures perform the same function of providing electrical access from a lower interconnect to the upper contact structure; modifying the interconnection structure in this way would lead to the predictable result of providing interconnection access. See MPEP 2143 I.B.
Regarding the limitation “a conformal sidewall liner surrounding a sidewall of the second contact plug”, Hsu discloses a semiconductor device (the device of FIG. 30, ¶ [0050]) wherein a sidewall liner (FIG. 30, first dielectric spacers 584 ¶ [0170]) surrounds a sidewall of a second contact plug (FIG. 30, through-memory-level contact via structures 588 ¶ [0170]), which is coupled to a first contact plug (FIG. 30, landing-pad-level metal line structure 788 ¶ [0169]) below. A person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Noda in view of Kim further in view of Hsu such that a sidewall liner surrounding a sidewall of the second contact plug, so that the second contact plug is provided with a barrier liner layer between itself and the gate electrodes.
Hsu does not explicitly state that the sidewall liner is conformal. However, selecting the method of depositing the liner material is a known necessity for forming the contact plug, and a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to try having the liner be conformal, in view of the fact that Hsu teaches that conformal and non-conformal deposition processes are both suitable for forming dielectric material layers (¶ [0072, 0081, 0111, 0139]), in order to deposit the liner to insulate the second contact plug. See MPEP 2143 I.E. Noda in view of Kim and Hsu does not explicitly teach that the pillar-type supporters are also void-free.
However, Otsu discloses a semiconductor device (the device of FIG. 51, “the third exemplary structure”, ¶ [0053-0067]), comprising void-free pillar-type supporters (dielectric support pillars may contain no voids, as described in ¶ [0249]). These void-free pillars are used for the same purpose as the support pillars of Noda, to support the structure of the device during the processing steps (Otsu ¶ [0249] and Noda ¶ [0057]). Therefore, Noda and Otsu being directed to the same field of endeavor, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to substitute the void-free pillars of Otsu in place of the pillars of Noda in view of Kim and Hsu, to achieve the predictable result of supporting the structure as both pillar-configurations have been demonstrated to be suitable for supporting the semiconductor structure during its processing. See MPEP 2143 I.B.
Regarding the limitations the void-free pillar-type supporters “penetrating a stepped structure of ends of the gate electrodes, wherein the gate contact plugs and the void-free pillar-type supporters are alternately arranged along the same axis extending in a first direction”, Noda in view of Kim, Hsu, and Otsu do not teach that feature. However, Eom discloses a semiconductor device (the device of FIGS. 2A-3B ¶ [0011-0012]) wherein pillar-type supporters (FIG. 2A and 3A, supporting structures SP ¶ [0049]) are penetrating a stepped structure of ends of gate electrodes (FIGS. 2A and 3A, contact region CTR is a stepped region having ends of word lines WL ¶ [0046-0047] which are penetrated by the supporting structures SP at the ends of the word lines), wherein gate contact plugs (FIGS. 2A and 3A, contact plugs WCT ¶ [0049]) and the pillar-type supporters are alternately arranged along the same axis extending in a first direction (FIG. 2A, as can be seen along line/axis A-A’ that extends in a first direction, supporting structures SP and contact plugs WCT are alternately arranged along that line/axis); Eom also teaches that the support pillars support the structure as the device is formed (¶ [0057]).
Noda, Kim, Hsu, Otsu, and Eom all pertain to the field of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, since Noda in view of Kim, Hsu, and Otsu discloses the claimed invention except for the void-free pillar-type supporters penetrating a stepped structure of ends of the gate electrodes wherein the gate contact plugs and the void-free pillar-type supporters are alternately arranged along the same axis extending in a first direction (the void-free pillar-type supporters being located at a more central position in the device in the disclosure of Noda), it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Noda in view of Kim, Hsu, and Otsu further in view of Eom such that the void-free pillar-type supporters penetrating a stepped structure of ends of the gate electrodes, wherein the gate contact plugs and the void-free pillar-type supporters are alternately arranged along the same axis extending in a first direction since Eom teaches that positioning the support pillars at ends of the gate electrodes in alternation with the gate contact plugs is a suitable configuration for supporting the structure of the device as it’s formed, and it has been held that rearranging parts of an invention involves only routine skill in the art In re Japikse, 86 USPQ 70.
Regarding claim 3, Noda in view of Kim, Hsu, Otsu, and Eom discloses the limitations of claim 1 as detailed above, but do not explicitly state that each of the void-free pillar-type supporters includes a stack of a conformal liner and a non-conformal layer.
However, Otsu does teach that the dielectric fill can be conformal or at least partly non-conformal, and that it may be void-free (¶ [0248-0249]). While a structure of a conformal liner and a non-conformal layer is not explicitly taught, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to use such a structure in view of the teaching of Otsu, since Otsu suggested that a partly conformal and partly non-conformal deposition may employed to form the dielectric pillars. A person of ordinary skill in the art would therefore have found it obvious to have each of the void-free pillar-type supporters includes a stack of a conformal liner and a non-conformal layer, because doing so would allow for a void-free formation with the relevant embodiment of the pillar-type supporters of Otsu, as the partially non-conformal deposition method taught by Otsu (Otsu “Deposition of the dielectric fill material… may be at least partly non-conformal” ¶ [0248]) would naturally include a conformal liner and a non-conformal layer.
Regarding claim 5, Noda in view of Kim, Hsu, Otsu, and Eom discloses the limitations of claim 1 as detailed above, and Noda further discloses that the gate-level dielectric layers and the gate electrodes are respectively positioned at same level along a vertical direction (FIGS. 2-3, word lines WL and gate-level dielectrics SN are respectively positioned at same levels along a vertical direction).
Regarding claim 6, Noda in view of Kim, Hsu, Otsu, and Eom discloses the limitations of claim 1 as detailed above, and Noda further discloses that the gate-level dielectric layers include silicon nitride, and the first dielectric layers and the second dielectric layers include silicon oxide (¶ [0048]).
Regarding claim 8, Noda in view of Kim, Hsu, Otsu, and Eom discloses the limitations of claim 1 as detailed above, and they further disclose that the edges of the gate electrodes (Eom FIG. 3A, outer edges of word lines WL) are formed in the stepped structure (Eom FIGS. 2A-3A, contact region CTR which is shown in FIG. 3A is the stepped structure wherein the edges of the gate electrodes are formed; an analogous structure can be seen in Noda FIG. 2).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Noda in view of Kim, Hsu, Otsu, and Eom as applied to claim 3 above, and further in view of US patent publication US 20190157283 A1 (Jung et al hereinafter Jung).
Noda in view of Kim, Hsu, Otsu, and Eom disclose the limitations of claim 3 as detailed above, but they do not further teach that the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS).
However, Jung discloses a semiconductor device (the device of FIGS. 2-5E ¶ [0011-0016]) comprising insulation pillars (FIGS. 2-3, insulation pillars IP ¶ [0061]) wherein the insulation pillars may comprise PETEOS (¶ [0062]). Noda, Otsu, and Jung all pertain to the field of memory devices. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Noda in view of Kim, Hsu, and Otsu further in view of Jung, such that the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS), in order to form the pillar-type supporters providing sufficient insulation and structural support in the device, because PETEOS has been demonstrated by Jung to be a suitable material to use in an insulation pillar.
Furthermore, “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Noda in view of Kim, Hsu, Otsu, and Eom as applied to claim 1 above, and further in view of US patent publication US 20210005629 A1 (Lim et al hereinafter Lim).
Noda in view of Kim, Hsu, Otsu, and Eom discloses the limitations of claim 1 as detailed above, but they do not further teach that the first contact plug, the second contact plug, and the gate contact plugs include tungsten.
However, Lim discloses a semiconductor device (the device of FIGS. 2-6) wherein a through-memory contact plug (FIG. 5, contact plugs 610b/610c ¶ [0079]) and gate contact plugs (FIG. 6, cell contact plugs 510 ¶ [0076]) may both include tungsten (¶ [0076, 0079]). Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Noda in view of Kim, Hsu, and Otsu further in view of Lim such that the first contact plug, the second contact plug, and the gate contact plugs include tungsten, since it has been shown by the prior art that tungsten is a suitable material to use for those features, and using a same material for those features would simplify the manufacturing (as opposed to using different materials for the different features).
Furthermore, “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813