DETAILED ACTION
This action is responsive to the following communications: Original Application filed on May 28, 2024. All references to this application refer to the U.S. Patent Application Publication No. 2025/0371403 A1.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this case. Claims 1 and 11 are the independent claims. Claims 1-20 are rejected.
Drawings
The drawings are objected to because figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the Examiner, the Applicants will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
INFORMATION ON HOW TO EFFECT DRAWING CHANGES
Replacement Drawing Sheets
Drawing changes must be made by presenting replacement sheets which incorporate the desired changes and which comply with 37 CFR 1.84. An explanation of the changes made must be presented either in the drawing amendments section, or remarks, section of the amendment paper. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). A replacement sheet must include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of the amended drawing(s) must not be labeled as “amended.” If the changes to the drawing figure(s) are not accepted by the Examiner, Applicants will be notified of any required corrective action in the next Office action. No further drawing submission will be required, unless Applicants are notified.
Identifying indicia, if provided, should include the title of the invention, inventor’s name, and application number, or docket number (if any) if an application number has not been assigned to the application. If this information is provided, it must be placed on the front of each sheet and within the top margin.
Annotated Drawing Sheets
A marked-up copy of any amended drawing figure, including annotations indicating the changes made, may be submitted or required by the Examiner. The annotated drawing sheet(s) must be clearly labeled as “Annotated Sheet” and must be presented in the amendment or remarks section that explains the change(s) to the drawings.
Timing of Corrections
Applicants are required to submit acceptable corrected drawings within the time period set in the Office action. See 37 CFR 1.85(a). Failure to take corrective action within the set period will result in ABANDONMENT of the application.
If corrected drawings are required in a Notice of Allowability (PTOL-37), the new drawings MUST be filed within the THREE MONTH shortened statutory period set for reply in the “Notice of Allowability.” Extensions of time may NOT be obtained under the provisions of 37 CFR 1.136 for filing the corrected drawings after the mailing of a Notice of Allowability.
Claim Objections
Claims 4 and 14 are objected to because of the following informalities:
Each of claims 4 and 14 recite “and/or.” Both claims should be amended to recite “or”
Appropriate corrections are required.
Examiner’s Note
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 11, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2020/0311220 A1, filed by Gunnels et al., on March 29, 2019, and published on October 1, 2020 (hereinafter Gunnels).
With respect to independent claim 1, Gunnels discloses a method, comprising:
Receiving, from a user, a quantum circuit; Gunnels discloses receiving a quantum circuit from a user (see paragraphs 0040-0042 [describing the receipt and initiation of an algorithm (quantum circuit) on a quantum processor, including an analysis of the algorithm for parameters such as timing, number of gates, assigned weights, etc.] and 0085-0086 [describing the transformation (transcompilation) of the algorithm into a quantum circuit]).
Identifying, in hardware, a QPU (quantum processing unit) for execution of the quantum circuit; Gunnels discloses identifying a QPU to execute the quantum circuit (see Fig. 1; see also, paragraphs 0058 [describing Fig. 1, including quantum processor 142] and 0074 [quantum processor is calibrated for executing the algorithm]).
Transpiling the quantum circuit; Gunnels discloses transcompiling the algorithm (see paragraphs 0022 [describing how the system transforms the algorithm into a quantum circuit] and 0025 [describing how the system transforms the algorithm into a quantum circuit]; see also, paragraphs 0074 and 0085-0086, described supra).
Determining, based on the transpiling, an excess qubit count X; Gunnels discloses analyzing the transpiled algorithm to determine the number of qubits required to perform the operations in view of the total number of qubits and, based on that determine the number of excess qubits (see paragraph 0090 [describing an example where the system analyzes the total number of qubits available (8), the number of qubits required to execute the circuit (5), and determine that there are 3 excess qubits which can be used to perform quantum error corrections (QEC)]).
Based on the excess qubit count X, performing either an error correction process with respect to the quantum circuit, or an error detection process with respect to the quantum circuit; Gunnels discloses determining the appropriate error correction technique based on the determined number of excess qubits (see paragraph 0091 [describing how the error correction selection component uses the determined excess number of qubits to select a QEC technique which produces the highest level of accuracy while also fitting the available qubits for QEC]).
With respect to dependent claim 6, Gunnels discloses the method as recited in claim 1, wherein the error correction process, or the error detection process, is performed while the quantum circuit is being executed by the QPU.
Gunnels discloses the error correction process is performed during runtime execution (see paragraphs 0092 [describing determination of error correction and execution during runtime]; see also, paragraph 0086, described supra, claim 1).
Independent claim 11, and its respective dependent claim 6, recite a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising the method performed by independent claim 1, and its respective dependent claim 6. Accordingly, independent claim 11, and its respective dependent claim 6, are rejected under the same rationales used to reject independent claim 1, and its respective dependent claim 6, which are incorporated herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicants are advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 3, 5, 7, 8, 12, 13, 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gunnels, in view of U.S. Patent Application Publication No. 2023/0186140 A1, filed by Su et al., on December 8, 2022, and published on June 15, 2023 (hereinafter Su).
With respect to dependent claim 2, Gunnels discloses the method as recited in claim 1, as described above.
Although Gunnels discloses determining the appropriate QEC technique to perform based on the determined number of excess qubits (see Gunnels, paragraph 0090, described supra, claim 1), Gunnels fails to expressly disclose the method wherein when the excess qubit count X meets or exceeds a threshold, the error correction process is performed.
However, Su teaches using threshold to determine whether to trigger error detection or error correction (see Su, Fig. 8; see also, Su, paragraphs 0021 [providing a method for determining whether to perform error correction or error detection based on various criteria], 0037 [describing the detection-correction operator which evaluates ancilla qubits to determine when to perform detection vs. correction], 0045 [if criteria are met, then error correction may be performed, if the criteria are not met then error correction may not be performed], 0053 [describing Fig. 8, which shows the circuit diagram including the error detection operator and the error-correction operator], and 0062 [the invention determines whether to perform detection vs. correction based on the determinations performed during runtime]).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Su before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate using various criteria to determine whether to perform error detection vs. performing error correction as taught by Su. One would have been motivated to make such a combination because this provides scalable fault tolerance in quantum computing, as taught by Su (see Su, paragraph 0006 [“Therefore, how to provide a scalable fault tolerance quantum computation becomes an urgent problem to be solved.”]).
With respect to dependent claim 3, Gunnels discloses the method as recited in claim 1, as described above.
Although Gunnels discloses determining the appropriate QEC technique to perform based on the determined number of excess qubits (see Gunnels, paragraph 0090, described supra, claim 1), Gunnels fails to expressly disclose the method wherein when the excess qubit count X fails to meet a threshold, the error detection process is performed.
However, Su teaches using threshold to determine whether to trigger error detection or error correction (see Su, Fig. 8; see also, Su, paragraphs 0021, 0037, 0045, 0053, and 0062, described supra, claim 2).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Su before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate using various criteria to determine whether to perform error detection vs. performing error correction as taught by Su. One would have been motivated to make such a combination because this provides scalable fault tolerance in quantum computing, as taught by Su (see Su, paragraph 0006, described supra, claim 2).
With respect to dependent claim 5, Gunnels discloses the method as recited in claim 1, as described above.
Although Gunnels discloses Steane coding as a method of error correction (see Gunnels, paragraph 0020 [generally describing types of QEC codes and the minimum required number of available qubits required to perform the particular types of QEC codes, including Shor, Steane, and Calderbank-Shor-Steane]), Gunnels fails to expressly disclose the method wherein the error correction process comprises performing Steane coding on logical qubits of the quantum circuit.
However, Su teaches performing Steane coding as the preferred method for QEC coding (see Su, paragraph 0047 [the codes used are primarily Steane codes and Reed-Muller codes]).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Su before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate using Steane codes as the QEC codes as taught by Su. One would have been motivated to make such a combination because this provides scalable fault tolerance in quantum computing, as taught by Su (see Su, paragraph 0006, described supra, claim 2).
With respect to dependent claim 7, Gunnels discloses the method as recited in claim 1, as described above.
Gunnels fails to expressly disclose the method wherein the error detection process is performed using one or more auxiliary qubits that have been added to the quantum circuit.
However, Su teaches using added auxiliary (ancilla) qubits to perform the error detection process (see Su, Fig. 8; see also, Su, paragraphs 0021, 0037, 0045, 0053, and 0062, described supra, claim 2).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Su before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate using auxiliary qubits to perform error detection as taught by Su. One would have been motivated to make such a combination because this provides scalable fault tolerance in quantum computing, as taught by Su (see Su, paragraph 0006, described supra, claim 2).
With respect to dependent claim 8, , Gunnels discloses the method as recited in claim 1, as described above.
Although Gunnels discloses determining the appropriate QEC technique to perform based on the determined number of excess qubits (see Gunnels, paragraph 0090, described supra, claim 1), Gunnels fails to expressly disclose the method wherein the error correction process comprises restoring respective intended states of one or more logical qubits of the quantum circuit.
However, Su teaches performing error correction by restoring intended states of logical qubits as part of QEC (see Su, Fig. 8; see also, Su, paragraphs 0021, 0037, 0045, 0053, and 0062, described supra, claim 2).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Su before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate restoring intended states of qubits as taught by Su. One would have been motivated to make such a combination because this provides scalable fault tolerance in quantum computing, as taught by Su (see Su, paragraph 0006, described supra, claim 2).
Dependent claims 12, 13, 15, 17, and 18 recite a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising the method performed by dependent claims 2, 3, 5, 7, and 8. Accordingly, dependent claims 12, 13, 15, 17, and 18, are rejected under the same rationales used to reject dependent claims 2, 3, 5, 7, and 8, which are incorporated herein.
Claims 4, 9, 10, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gunnels, in view of U.S. Patent No. 11,416,762 B1, issued to Nevah et al., on August 16, 2022, and filed on April 14, 2022 (hereinafter Nevah).
With respect to dependent claim 4, Gunnels discloses the method as recited in claim 1, as described above.
Gunnels fails to expressly disclose the method wherein a real time analysis is performed to determine which logical qubit(s) of the quantum circuit are most valuable, relative to other logical qubit(s) of the quantum circuit, to detect [or] correct errors in.
However, Nevah teaches analyzing the quantum circuit to determine which, if any, qubits have more significant contributions to the outcome, and therefore, corrections to those qubits will have greater impact on the solution (see Nevah, col. 6, lines 9-13 [it may be desired to obtain an optimal allocation of logical and physical qubits that minimizes the total error taking into account the role and priority of different qubits] and col. 9, lines 57-63 [because some qubits may be manipulated by more gates than others, or used as output qubits, they have a stronger effect on the output, and thus error rates of those qubits may be more significant compared to other qubits]).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Nevah before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate determination of most significant qubits as taught by Nevah. One would have been motivated to make such a combination because this helps to achieve the highest, fault-tolerant QEC on quantum circuits, as taught by Nevah (see Nevah, col. 1, lines 22-26 [“Quantum Error Correction (QEC) may be configured to protect quantum information from errors due to decoherence and other quantum noise. Quantum error correction is essential if one is to achieve fault-tolerant quantum computation that can handle noise on stored quantum information.”]).
With respect to dependent claim 9, Gunnels discloses the method as recited in claim 1, as described above.
Gunnels fails to expressly disclose the method wherein the quantum circuit is one of a group of received quantum circuits, and the QPU is a smallest QPU that is able to execute any of the quantum circuits individually.
However, Nevah teaches analyzing a plurality of different quantum circuit arrangements of different physical and logical qubits sizes for a received group of quantum circuits and the QPU is the smallest that can execute all of the received quantum circuits (see Nevah, col. 5, lines 29-56 [describing a first solution for selecting an assignment of physical qubits to logical qubits to create multiple quantum circuits capable of the same operation which are all executed on the same QP], col. 8, lines 6-28 [the logical representation of qubits may be implementable on a plurality of alternative physical representations of qubits], and col. 12, lines 9-37 [describing how the solver searches for different arrangements of assigned physical to logical qubits to find optimal arrangements that can be executed by the QPU]).
Accordingly, it would have been obvious to one of ordinary skill in the art, having the teachings of Gunnels and Nevah before him before the effective filing date of the claimed invention, to modify the method of Gunnels to incorporate multiple arrangements of qubits and a QPU capable of executing all of the different arrangements as taught by Nevah. One would have been motivated to make such a combination because this helps to achieve the highest, fault-tolerant QEC on quantum circuits, as taught by Nevah (see Nevah, col. 1, lines 22-26, described supra, claim 4).
With respect to dependent claim 10, Gunnels, as modified by Nevah, teaches the method as recited in claim 9, as described above.
Nevah further teaches the method wherein the quantum circuits are all run together on the QPU, and a total cost to run respective groups of shots of all the quantum circuits is determined based on a number of shots performed for a single one of the quantum circuits as a fraction of a total of all the shots for all the quantum circuits.
Nevah further teaches running all the different quantum circuits in parallel and determining a total cost function as a ratio of shots/circuit to total shots/all circuits (see Nevah, col. 28, lines 3-45 [describing the determination of cost metrics, such as value per qubit, of each circuit and the total cost for all circuits, and determining an optimal cost function that minimizes the cost functions]).
Dependent claims 14, 19, and 20 recite a non-transitory storage medium having stored therein instructions that are executable by one or more hardware processors to perform operations comprising the method performed by dependent claims 4, 9, and 10. Accordingly, dependent claims 14, 19, and 20, are rejected under the same rationales used to reject dependent claims 4, 9, and 10, which are incorporated herein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure. See PTO-892.
It is noted that any citation to specific pages, columns, figures, or lines in the prior art references any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331-33, 216 USPQ 1038-39 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to ERIC J. BYCER whose telephone number is (571) 270-3741. The Examiner can normally be reached Monday - Thursday 9am-6pm, and alternate Fridays 9am-5pm.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, Applicants are encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/InterviewPractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, MATT ELL can be reached on (571) 270-3264. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC J. BYCER/
Primary Examiner
Art Unit 2141
Prosecution Insights