Office Action Predictor
Last updated: April 16, 2026
Application No. 18/676,296

TRANSMISSION LINE POWER DIVIDERS AND POWER COMBINERS WITH MATCHED PORTS

Non-Final OA §103
Filed
May 28, 2024
Examiner
OUTTEN, SAMUEL S
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
L3 Technologies, INC.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
499 granted / 634 resolved
+10.7% vs TC avg
Strong +21% interview lift
Without
With
+20.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
34 currently pending
Career history
668
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
48.6%
+8.6% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 634 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-9 & 12-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. (US Patent 5662816) As per claim 1: Andry discloses in Figs. 1-5 & 8: A circuit, comprising: an input arm (microstrip trace MT1 connected to connector point 1 CP1) defined as an electrically-conductive transmission line (microstrip trace) on or within a printed circuit board (PCB) (printed circuit board CB1); multiple output arms (respective microstrip traces MT1 connected to connector points CP2, CP3, & CP4) electrically coupled to the input arm, each of the multiple output arms being defined as a separate electrically-conductive transmission line on or within the PCB (as seen in Fig. 1); multiple impedance transformers (quarter-wavelength traces MT2-4, col. 5 line 52-col. 6 line 2) defined as separate respective electrically-conductive transmission lines on or within the PCB (defined as Microstrip traces and shown in Fig. 1); and at least one resistive shunt (terminating resistors R11-R13, col. 4 lines 61-66) electrically coupled between each one of the multiple output arms and a ground plane of the PCB (ground is provided through connections to ground plane GP1 through via holes VH2, col. 3 lines 52-67), the resistive shunt being part of the board (col. 4 lines 61-66), and each of the impedance transformers being electrically coupled between a respective one of the resistive shunts and the input arm (as seen in Fig. 5). Andry does not disclose: the resistive shunt being one or more electrically-conductive transmission lines defined on or within the PCB. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the resistors of Andry as electrically-conductive transmission lines defined on or within the PCB as an art-recognized method of forming resistors and as suggested by Andry in the resistors being part of the board (col. 4 lines 61-66) As a consequence of the combination, the at least one resistive shunt is one or more electrically-conductive transmission lines defined on or within the PCB. As per claim 2: Andry discloses in Figs. 1-5 & 8: the at least one resistive shunt comprises a first resistive shunt (1R11) and a second resistive shunt (R12); where the multiple output arms comprise a first output arm (MT1 connected to CP2) and a second output arm (MT1 connected to CP3); where the multiple impedance transformers comprise a first impedance transformer (MT2) electrically coupled between the first output arm and the first resistive shunt, and a second impedance transformer (MT3) electrically coupled between the second output arm and the second resistive shunt; where the first resistive shunt is electrically coupled between the first impedance transformer and the ground plane (as seen in Fig. 5); and where the second resistive shunt is electrically coupled between the second impedance transformer and the ground plane (as seen in Fig. 5). As per claim 3: Andry discloses in Figs. 1-5 & 8: the circuit further comprises an additional shunt (R13) electrically coupled between a first circuit node and a second circuit node, the first circuit node being positioned between the first impedance transformer and the first resistive shunt, and the second circuit node being positioned between the second impedance transformer and the second resistive shunt (R13 is connected through MT23 to the virtual ground node, connected between the first and second circuit nodes). As per claims 4 & 23: Andry discloses in Figs. 1-5 & 8: the at least one resistive shunt comprises multiple separate resistive shunts (resistors R11, R12, & R13) that each correspond to one of the multiple output arms (arms connected to connector points 1, 2, & 3, respectively); where each of the multiple separate resistive shunts is electrically coupled at a first end to a corresponding one of the multiple impedance transformers and electrically coupled at a second end to the ground plane of the PCB with each of the multiple impedance transformers being electrically coupled between a corresponding one of the multiple output arms and a corresponding one of the multiple separate resistive shunts (as seen in Figs. 1, 5, & 12). As per claim 5: Andry discloses in Figs. 1-5 & 8: each of the multiple separate resistive shunts is electrically coupled between a corresponding one of the multiple impedance transformers and a corresponding via that is electrically coupled to at least one ground plane layer of the ground plane of the PCB (col. 3 lines 52-67). As per claim 6: Andry discloses in Figs. 1-5 & 8: each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained on the PCB. Andry does not disclose: each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained within the PCB. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the circuit of Andry using stripline technology as opposed to microstrip technology as an art-recognized alternative/equivalent method of forming transmission lines including an upper dielectric substrate and a ground plane over the dielectric substrate and ground plane of transmission lines. As a consequence of the combination, each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained within the PCB. As per claim 7: Andry discloses in Figs. 1-5 & 8: the circuit implements a power divider circuit having no discrete resistive elements with the possible exception of the resistors R11, R12, and R13; where the input arm comprise an input port to the power divider; and where the multiple output arms comprise multiple respective output ports of the power divider. As a consequence of the combination of claim 1, the resistors R11, R12, and R13 are formed as transmission lines, and not as discrete resistive elements. As per claim 8: Andry discloses in Figs. 1-5 & 8: the multiple impedance transformers (quarter-wavelength traces MT2-4, col. 5 line 52-col. 6 line 2) has a length that is one quarter of a wavelength (λ) at the fundamental frequency (f0); and where a resistance value of the resistive shunt is equal to a characteristic impedance (Z0) at the fundamental frequency (f0) of the circuit (characteristic impedance of 50 Ohms, as seen in Fig. 5). As per claims 9 & 24: Andry discloses in Figs. 1-5 & 8: the circuit further comprises the at least one resistive shunt electrically coupled between each one of the multiple output arms (as seen in Fig. 5) and the ground plane of the PCB (ground is provided through connections to ground plane GP1 through via holes VH2, col. 3 lines 52-67), and each of the impedance transformers being electrically coupled between a respective one of the multiple output arms and a respective one of the resistive shunts (as seen in Fig. 5). Andry does not disclose: the resistive shunt being one or more electrically-conductive transmission lines defined on or within the PCB. As a consequence of the combination of claims 1 & 17, the resistive shunt is one or more electrically-conductive transmission lines defined on or within the PCB. As per claim 12: Andry discloses in Figs. 1-6 & 8: A system, comprising: a planar printed circuit board (PCB) (printed circuit board CB1); a power divider circuit (N-way power divider circuit where N=3 for Figs. 1-10 & more for Figs. 11-16) comprising: an input arm (microstrip trace MT1 connected to connector point 1 CP1) defined as an electrically-conductive transmission line (microstrip trace) on or within the PCB (printed circuit board CB1) and the input arm providing an input port for the power divider circuit (receives an input signal, col. 4 lines 25-48), multiple output arms (respective microstrip traces MT1 connected to connector points CP2, CP3, & CP4) electrically coupled to the input arm, each of the multiple output arms being defined as a separate electrically-conductive transmission line on or within the PCB (as seen in Fig. 1) and each of the multiple output arms providing a separate and different output port for the power divider circuit (distributes the output, col. 4 lines 25-48), and multiple impedance transformers (quarter-wavelength traces MT2-4, col. 5 line 52-col. 6 line 2) defined as separate respective electrically-conductive transmission lines on or within the PCB (defined as Microstrip traces and shown in Fig. 1); and at least one power source (source of input signal, col. 4 lines 25-48 or amplifiers AM1-N); where the power divider circuit further comprises at least one resistive shunt (terminating resistors R11-R13, col. 4 lines 61-66) electrically coupled between each one of the multiple output arms and a ground plane of the PCB (ground is provided through connections to ground plane GP1 through via holes VH2, col. 3 lines 52-67), the resistive shunt being part of the board (col. 4 lines 61-66), and each of the impedance transformers being electrically coupled between a respective one of the resistive shunts and the input arm (as seen in Fig. 5); and where either one of: the at least one power source (source of input signal, col. 4 lines 25-48) is electrically coupled to the input port of the power divider circuit and providing input power to the input port of the power divider circuit (DCI of Fig. 6), and a separate and different additional circuit (amplifiers AM1-N) electrically-coupled to each given one of the separate and different output ports of the power divider circuit and receiving a portion of the provided input power from the given one of the separate and different output ports of the power divider circuit (col. 4 lines 25-48), or the at least one power source (amplifiers AM1-N) comprises a separate and different power source electrically-coupled to each given one of the separate and different output ports of the power divider circuit DC2 of Fig. 6) and providing input power to the given one of the separate and different output ports of the power divider circuit, and an additional circuit (receiver of output signal col. 4 lines 25-48) electrically-coupled to the input port of the power divider circuit and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit. Andry does not disclose: the resistive shunt being one or more electrically-conductive transmission lines defined on or within the PCB, that the signal input is a separate power source or an additional circuit electrically-coupled to the input port of the power divider and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the resistors of Andry as electrically-conductive transmission lines defined on or within the PCB as an art-recognized method of forming resistors and as suggested by Andry in the resistors being part of the board (col. 4 lines 61-66) As a consequence of the combination, the at least one resistive shunt is one or more electrically-conductive transmission lines defined on or within the PCB. It would have been further obvious for the input signal IN1 to be provided by a power source, as input signals inherently require a source of power for generation and transmission, as is well understood in the art, and for the output signal to be received by an additional circuit electrically-coupled to the input port of the power divider and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit, as per the function of a circuit wherein electrical energy is provided for desired functions, as is well understood in the art. As per claim 13: Andry discloses in Figs. 1-6 & 8: the at least one power source is electrically coupled to the input port of the power divider circuit and providing input power to the input port of the power divider circuit (providing an input signal, as per DCI of Fig. 6, col. 4 lines 61-66), and a separate and different additional circuit (amplifiers AM1-N) electrically-coupled to each given one of the separate and different output ports of the power divider circuit and receiving a portion of the provided input power from the given one of the separate and different output ports of the power divider circuit (col. 4 lines 61-66). Andry is silent regarding the input signal being provided by at least one power source. As a consequence of the combination of claim 12, the input signal is provided by at least one power source. As per claim 14: Andry discloses in Figs. 1-6 & 8: the at least one power source comprises a separate and different power source (AM1-N) electrically-coupled to each given one of the separate and different output ports of the power divider circuit and providing input power to the given one of the separate and different output ports of the power divider circuit (DC2 of Fig. 6, col. 4 lines 61-66), and an additional circuit (receiver of output signal col. 4 lines 25-48) electrically-coupled to the input port of the power divider circuit and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit. Andry is silent regarding the output signal being received by an additional circuit. As a consequence of the combination of claim 12, the output signal is received by an additional circuit. As per claim 15: Andry discloses in Figs. 1-5 & 8: each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained on the PCB, the circuit implements a power divider circuit having no discrete resistive elements with the possible exception of the resistors R11, R12, and R13. Andry does not disclose: all circuit components of the power divider circuit are implemented in at least one internal layer of PCB; where the power divider circuit comprises no discrete resistive elements; and where the at least one power source is mounted to an external surface of the PCB in a position that overlies or underlies the power divider circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the circuit of Andry using stripline technology as opposed to microstrip technology as an art-recognized alternative/equivalent method of forming transmission lines including an upper dielectric substrate and a ground plane over the dielectric substrate and ground plane of transmission lines. As a consequence of the combination, each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line implemented in at least one internal layer of PCB. As a consequence of the combination of claim 12, the resistors R11, R12, and R13 are formed as transmission lines, and not as discrete resistive elements. It would be further obvious for the at least one power source is mounted to an external surface of the PCB in a position that overlies or underlies the power divider circuit to provide the benefit of providing a compact structure for the circuit of Fig. 6 of Andry et al. and to reduce the distance between components, as is well understood in the art. As per claim 16: Andry discloses in Figs. 1-5 & 8: the at least one resistive shunt of the power divider circuit comprises multiple separate resistive shunts (resistors R11, R12, & R13) that each correspond to one of the multiple output arms (arms connected to connector points 1, 2, & 3, respectively); where each of the multiple separate resistive shunts is electrically coupled at a first end to a corresponding one of the multiple impedance transformers and electrically coupled at a second end to the ground plane of the PCB with each of the multiple impedance transformers being electrically coupled between a corresponding one of the multiple output arms and a corresponding one of the multiple separate resistive shunts (as seen in Figs. 1, 5, & 12). As per claim 17: Andry discloses in Figs. 1-6 & 8: A method, comprising either one of: providing input power (input signal, for DCI of Fig. 6) to an input port of a power divider circuit, and receiving a portion of the provided input power from each given one of multiple separate and different output ports of the power divider circuit (col. 4 lines 25-48); or providing input power (amplifiers AM1-N, for DC2 of Fig. 6) to each given one of the multiple separate and different output ports of the power divider circuit, and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the multiple separate and different output ports of the power divider circuit (col. 4 lines 25-48); where the power divider circuit comprises: an input arm (microstrip trace MT1 connected to connector point 1 CP1) comprising the input port and defined as an electrically-conductive transmission line (microstrip trace) on or within a printed circuit board (PCB) (printed circuit board CB1), multiple output arms (respective microstrip traces MT1 connected to connector points CP2, CP3, & CP4) comprising the multiple respective output ports of the power divider and being electrically coupled to the input arm, each of the multiple output arms being defined as a separate electrically-conductive transmission line on or within the PCB (as seen in Fig. 1), multiple impedance transformers (quarter-wavelength traces MT2-4, col. 5 line 52-col. 6 line 2) defined as separate respective electrically-conductive transmission lines on or within the PCB (defined as Microstrip traces and shown in Fig. 1), and at least one resistive shunt (terminating resistors R11-R13, col. 4 lines 61-66) electrically coupled between each one of the multiple output arms and a ground plane of the PCB (ground is provided through connections to ground plane GP1 through via holes VH2, col. 3 lines 52-67), the resistive shunt being part of the board (col. 4 lines 61-66), and each of the impedance transformers being electrically coupled between a respective one of the resistive shunts and the input arm (as seen in Fig. 5). Andry does not disclose: the resistive shunt being one or more electrically-conductive transmission lines defined on or within the PCB. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the resistors of Andry as electrically-conductive transmission lines defined on or within the PCB as an art-recognized method of forming resistors and as suggested by Andry in the resistors being part of the board (col. 4 lines 61-66) As a consequence of the combination, the at least one resistive shunt is one or more electrically-conductive transmission lines defined on or within the PCB. As per claim 18: Andry discloses in Figs. 1-6 & 8: providing the input power to the input port of the power divider circuit from at least one power source that is electrically coupled to the input port of the power divider circuit (providing an input signal, as per DCI of Fig. 6, col. 4 lines 61-66), and receiving a portion of the provided input power from each given one of the multiple separate and different output ports of the power divider circuit in a corresponding respective separate additional circuit (amplifiers AM1-N) that is electrically-coupled to the given one of the separate and different output ports of the power divider circuit (col. 4 lines 61-66). Andry is silent regarding the input signal being provided by at least one power source. It would have been further obvious for the input signal IN1 to be provided by at least one power source, as input signals inherently require a source of power for generation and transmission, as is well understood in the art. As per claim 19: Andry discloses in Figs. 1-6 & 8: each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained on the PCB, the circuit implements a power divider circuit having no discrete resistive elements with the possible exception of the resistors R11, R12, and R13. Andry does not disclose: all circuit components of the power divider circuit are implemented in at least one internal layer of PCB; where the power divider circuit comprises no discrete resistive elements; and where at least one of the power source or at least a portion of the corresponding respective separate additional circuits is mounted to an external surface of the PCB in a position that is coextensive with at least a portion of the power divider circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the circuit of Andry using stripline technology as opposed to microstrip technology as an art-recognized alternative/equivalent method of forming transmission lines including an upper dielectric substrate and a ground plane over the dielectric substrate and ground plane of transmission lines. As a consequence of the combination, each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line implemented in at least one internal layer of PCB. As a consequence of the combination of claim 12, the resistors R11, R12, and R13 are formed as transmission lines, and not as discrete resistive elements. It would be further obvious for at least one of the power source or at least a portion of the corresponding respective separate additional circuits is mounted to an external surface of the PCB in a position that is coextensive with at least a portion of the power divider circuit to provide the benefit of providing a compact structure for the circuit of Fig. 6 of Andry et al. and to reduce the distance between components, as is well understood in the art. As per claim 20: Andry discloses in Figs. 1-6 & 8: providing the input power to each given one of the multiple separate and different output ports of the power divider circuit from a corresponding separate and different power source (amplifiers AM1-N) electrically-coupled to the given one of the separate and different output ports of the power divider circuit; and receiving a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit in an additional circuit (receiver of output signal col. 4 lines 25-48) that is electrically-coupled to the input port of the power divider circuit. Andry is silent regarding the output signal being received by an additional circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art for the output signal to be received by an additional circuit electrically-coupled to the input port of the power divider and receiving at the input port of the power divider circuit a combination of the input power provided to each given one of the separate and different output ports of the power divider circuit, as per the function of a circuit wherein electrical energy is provided for desired functions, as is well understood in the art. As per claim 21: Andry discloses in Figs. 1-6 & 8: each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line contained on the PCB, the circuit implements a power divider circuit having no discrete resistive elements with the possible exception of the resistors R11, R12, and R13. Andry does not disclose: all circuit components of the power divider circuit are implemented in at least one internal layer of PCB; where the power divider circuit comprises no discrete resistive elements; and where at least a portion of the corresponding separate and different power sources or the additional circuit is mounted to an external surface of the PCB in a position that is coextensive with at least a portion of the power divider circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the circuit of Andry using stripline technology as opposed to microstrip technology as an art-recognized alternative/equivalent method of forming transmission lines including an upper dielectric substrate and a ground plane over the dielectric substrate and ground plane of transmission lines. As a consequence of the combination, each of the input arm, each of the multiple output arms and each of the multiple impedance transformers are defined as an electrically-conductive transmission line implemented in at least one internal layer of PCB. As a consequence of the combination of claim 12, the resistors R11, R12, and R13 are formed as transmission lines, and not as discrete resistive elements. It would be further obvious for at least a portion of the corresponding separate and different power sources or the additional circuit to be mounted to an external surface of the PCB in a position that is coextensive with at least a portion of the power divider circuit to provide the benefit of providing a compact structure for the circuit of Fig. 6 of Andry et al. and to reduce the distance between components, as is well understood in the art. As per claim 22: Andry discloses in Figs. 1-6 & 8: the at least one resistive shunt comprises a first resistive shunt (1R11) and a second resistive shunt (R12); where the multiple output arms comprise a first output arm (MT1 connected to CP2) and a second output arm (MT1 connected to CP3); where the multiple impedance transformers comprise a first impedance transformer (MT2) electrically coupled between the first output arm and the first resistive shunt, and a second impedance transformer (MT3) electrically coupled between the second output arm and the second resistive shunt; where the first resistive shunt is electrically coupled between the first impedance transformer and the ground plane (as seen in Fig. 5); where the second resistive shunt is electrically coupled between the second impedance transformer and the ground plane (as seen in Fig. 5); and where the power divider circuit further comprises an additional shunt (R13) electrically coupled between a first circuit node and a second circuit node, the first circuit node being positioned between the first impedance transformer and the first resistive shunt, and the second circuit node being positioned between the second impedance transformer and the second resistive shunt (R13 is connected through MT23 to the virtual ground node, connected between the first and second circuit nodes). Allowable Subject Matter Claims 10-11 & 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the combination of limitations found in claims 10 & 25 in combination with the limitation of their respective parent claims were not disclosed or rendered obvious over the prior art of record, or the closest related prior art of Andry et al. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL S OUTTEN whose telephone number is (571)270-7123. The examiner can normally be reached M-F: 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Samuel S Outten/Primary Examiner, Art Unit 2843
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Prosecution Timeline

May 28, 2024
Application Filed
Jan 28, 2026
Non-Final Rejection — §103
Apr 01, 2026
Response Filed

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