DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election of Claims 1-7, without traverse, has been acknowledged. Claims 1-10 remain pending. Claims 8-10 are withdrawn from consideration.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Structure with Field Plate and Multiple Dielectric Layers and Method of Forming the Same.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al (US 2022/0376061).
Regarding Claim 1, Zhao et al discloses a semiconductor structure (semiconductor device 100A [0018] Fig 1C and Fig 2), comprising:
a substrate (substrate 102 [0019] Fig 1C);
a semiconductor layer (nitride-based semiconductor layer 104 and 106 [0019] Fig 1C and Fig 2) on the substrate (102 Fig 1C and Fig 2);
a gate structure (gate structure 110 [0024] Fig 1C and Fig 2) on the semiconductor layer (104 and 106 Fig 1C and Fig 2);
a first dielectric layer (passivation layer 116 [0019] Fig 1C and Fig 2) continuously extending on the gate structure (110 Fig 1C and Fig 2) and the semiconductor layer (104 and 106 Fig 1C and Fig 2), wherein the first dielectric layer (116 Fig 1C and Fig 2) comprises a first portion (shown in annotated Fig 2), a second portion (shown in annotated Fig 2), a third portion (shown in annotated Fig 2), and a fourth portion (shown in annotated Fig 2), and
the third portion (shown in annotated Fig 2) and the fourth portion (shown in annotated Fig 2) are on an upper surface of the gate structure (110 Fig 1C and Fig 2);
an etch stop layer (field plate 122 [0018] is capable of functioning as an etch stop layer Fig 1C and Fig 2) on at least the first portion (shown in annotated Fig 2) and the fourth portion (shown in annotated Fig 2) of the first dielectric layer (116 Fig 1C and Fig 2);
a second dielectric layer (passivation layer 118 [0030] Fig 1C and Fig 2) on the etch stop layer (122 Fig 1C and Fig 2); and
a field plate (field plate 124 [0018] Fig 1C and Fig 2) comprising a first field plate portion (shown in annotated Fig 2) on the second dielectric layer (118 Fig 1C and Fig 2),
a second field plate portion (shown in annotated Fig 2) and
a third field plate portion (shown in annotated Fig 2) respectively on the second portion (shown in annotated Fig 2) and the third portion (shown in annotated Fig 2) of the first dielectric layer (116 Fig 1C and Fig 2), and
a fourth field plate portion (shown in annotated Fig 2) on the second dielectric layer (118 Fig 1C and Fig 2),
wherein a first distance (shown in annotated Fig 2) between a lower surface of the first field plate portion (shown in annotated Fig 2) and the semiconductor layer (104 and 106 Fig 1C and Fig 2) is larger than a second distance (shown in annotated Fig 2) between a lower surface of the second field plate portion (shown in annotated Fig 2) and the semiconductor layer (104 and 106 Fig 1C and Fig 2), and
a third distance (shown in annotated Fig 2) between a lower surface of the third field plate portion (shown in annotated Fig 2) and the semiconductor layer (104 and 106 Fig 1C and Fig 2) is smaller than a fourth distance (shown in annotated Fig 2) between a lower surface of the fourth field plate portion (shown in annotated Fig 2) and the semiconductor layer (104 and 106 Fig 1C and Fig 2).
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Regarding Claim 2, Zhao et al discloses the limitations of claim 1 as explained above. Zhao et al further discloses
wherein the field plate (field plate 124 [0018] Fig 1C and Fig 2) extends continuously on the first dielectric layer (116 Fig 1C and Fig 2) and the second dielectric layer (118 Fig 1C and Fig 2).
Regarding Claim 3, Zhao et al discloses the limitations of claim 1 as explained above. Zhao et al further discloses
wherein a projection of the second dielectric layer (118 Fig 1C and Fig 2) on the substrate (102 Fig 1C) along a vertical direction of the substrate (102 Fig 1C) overlaps with a projection of the first portion (shown in annotated Fig 2) and the fourth portion (shown in annotated Fig 2) of the first dielectric layer (116 Fig 1C and Fig2) on the substrate (102 Fig 1C) along the vertical direction of the substrate (102 Fig 1C), and
the projection of the second dielectric layer (118 Fig 1C and Fig 2) on the substrate (102 Fig 1C) along the vertical direction of the substrate (102 Fig 1C) does not overlap with a projection of the second portion (shown in annotated Fig 2) and the third portion (shown in annotated Fig 2) of the first dielectric layer (shown in annotated Fig 2) on the substrate (102 Fig 1C) along the vertical direction of the substrate (102 Fig 1C).
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Regarding Claim 4, Zhao et al discloses the limitations of claim 1 as explained above. Zhao et al further discloses
wherein the first field plate portion (shown above in annotated Fig 2) and the second field plate portion (shown above in annotated Fig 2) are beside a same side of the gate structure (110 Fig 1C and Fig 2), and the second field plate portion (shown above in annotated Fig 2) is closer to the gate structure (110 Fig 1C and Fig 2) than the first field plate portion (shown above in annotated Fig 2).
Regarding Claim 5, Zhao et al discloses the limitations of claim 4 as explained above. Zhao et al further discloses
wherein the third field plate portion (shown above in annotated Fig 2) is closer to the first field plate portion (shown above in annotated Fig 2) and the second field plate portion (shown above in annotated Fig 2) than the fourth field plate portion (shown above in annotated Fig 2).
Regarding Claim 6, Zhao et al discloses the limitations of claim 1 as explained above. Zhao et al further discloses
further comprising a third dielectric layer (passivation layer 120 [0019] Fig 1C and Fig 2) on the first dielectric layer (116 Fig 1C and Fig 2) and the second dielectric layer (118 Fig 1C), wherein the field plate (124 Fig 1C and Fig 2) is on the third dielectric layer (120 Fig 1C and Fig 2).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7:
Regarding Claim 7, Zhao et al discloses the limitations of claim 1 as explained above. Zhao et al (US 2022/0376061) further discloses
an upper surface of the third portion (shown in annotated Fig 2) of the first dielectric layer (116 Fig 1C and Fig 2) is lower (shown in annotated Fig 2) than an upper surface of the fourth portion (shown in annotated Fig 2) of the first dielectric layer (116 Fig 1C and Fig 2).
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The reason for the indication of allowability of Claim 7 is the inclusion of
wherein an upper surface of the second portion of the first dielectric layer is lower than an upper surface of the first portion of the first dielectric layer.
Specifically, it can be observed in annotated Fig 2 of Zhao et al that the upper surface of the second portion of the first dielectric layer (116 Fig 1C and Fig 2) is at the same height as the upper surface of the first portion of the first dielectric layer (116 Fig 1C and Fig2), and there does not appear to be a reasonable interpretation to suggest otherwise. Further, should another reference be found that discloses this limitation, it would not be obvious to a person of ordinary skill in the art to combine the references and make this alteration to Zhao et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hutzler et al (US 2017/0330941) which discloses a semiconductor device with a structured etch stop layer [0005], and Bothe et al (US 2020/0395474) which discloses a HEMT device with a field plate on the second insulating layer [0019].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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