DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-2, 9-10, 12-14, 16-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen U.S. Patent Application Publication 20140262464 A1 (the ‘464 reference, cited in a related PCT application and matured into U.S. Patent 9,380,705 B2).
The reference discloses in Figs. 2, 4A and related text an insulating chip and a signal transmission device as claimed.
Referring to claim 1, the ‘464 reference discloses an insulating chip (240; 420, para [15, 24] (paragraph(s) [0015], [0024])), comprising:
a substrate (underlying layer 246/234;428, para [17,26]);
an element insulation layer (dielectric 248; 434/426, para [15, 26]) arranged on the substrate (246/234;428); and
a capacitor including a first electrode plate (trace 242; 422, “as capacitor plate”) and a second electrode plate (trace 244; 424, “as capacitor plate”, para [15]) embedded in the element insulation layer (248; 434/426),
wherein the first electrode plate (242; 422) and the second electrode plate (244; 424) are opposed to each other in a first direction (horizontal direction) that is a direction orthogonal to a thickness-wise direction of the element insulation layer (248; 434/426).
Referring to claim 2, Figs. 2 and 4A depicts that the first electrode plate (242; 422) and the second electrode plate (244; 424) are each flat and have a thickness extending in the first direction.
Referring to claim 9, Fig. 2 clearly depicts that a distance between the first electrode plate (242) and the second electrode plate (244) in the first direction (the horizontal direction) is greater than a thickness of the element insulation layer (248) (read also para [15], wherein the reference discloses that the distance between the first electrode and the second electrode can be varied as needed).
Referring to claim 10, Fig. 4A depicts that (portion 426 of) the element insulation layer (434/426) is arranged between the first electrode plate (422) and the substrate (428) and between the second electrode plate (424) and the substrate (428).
Referring to claim 12, the reference further discloses that
the first electrode plate (324, Fig. 3B, which is mistakenly labeled as 334, para [23]) and the second electrode plate (322, Fig. 3B, which is mistakenly labeled as 332) are each tubular and have an axis extending in the thickness-wise direction (into-the-paper direction) of the element insulation layer (not labeled in Fig. 3B), the axis of the first electrode plate coinciding with the axis of the second electrode plate,
a dimension of the first electrode plate (324) in a direction orthogonal to the thickness-wise direction of the element insulation layer is larger than a dimension of the second electrode plate (322) in the direction orthogonal to the thickness-wise direction of the element insulation layer, and
the second electrode plate (322) is arranged inside the first electrode plate (324) and opposed to the first electrode plate (324) in the direction orthogonal to the thickness-wise direction of the element insulation layer.
Referring to claim 13, the reference further discloses that the first electrode plate (324) and the second electrode plate (322) are each circularly tubular (see Fig. 3B).
Referring to claim 14, although not explicitly disclosed, the first electrode plate and the second electrode plate are notoriously formed from a material including at least one of copper, aluminum, and tungsten.
Referring to claim 16, Fig. 2 depicts that the insulating chip (240) is mounted on a mount frame (258, para [21]) that is electrically floating, meeting the claim limitation “in a state insulated from the mount frame or the insulating chip is mounted on a mount frame that is electrically floating”.
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a signal transmission device, comprising:
a first chip (212; 410, para [13, 24]) including a first circuit;
an insulating chip (240; 420); and
a second chip (transceiver 222; TX/RX 2 (222), para [13]) including a second circuit configured to perform at least one of reception of a signal and transmission of a signal with the first circuit through the insulation chip,
wherein the insulating chip (240; 420) includes
a substrate (246/234;428),
an element insulation layer (248; 434/426) arranged on the substrate, and
a capacitor including a first electrode plate (242; 422) and a second electrode plate (244; 424) embedded in the element insulation layer (248; 434/426), and
the first electrode plate (242; 422) and the second electrode plate (244; 424) are opposed to each other in a first direction that is a direction orthogonal to a thickness-wise direction of the element insulation layer (248; 434/426).
Referring to claim 19, Fig. 2 depicts:
a first mount frame (216, para [13]) on which the first chip (212) is mounted;
a second mount frame (226, para [14]) on which the second chip (222) is mounted; and
a third mount frame (258, para [21]) on which the insulation chip is mounted,
wherein the third mount frame (258) is electrically floating (not electrically connecting) with respect to both the first mount frame (216) and the second mount frame (226).
Referring to claim 20, Fig. 3B depicts that:
the signal transmission device is configured to transmit a signal from the first circuit (of the first chip 212) toward the second circuit (of the second chip 222) through the capacitor (comprising capacitor plates 242 and 244 in Fig. 2, comprising capacitor plates 322 & 324, which are mistakenly labeled as 332 & 334, para [23], and 326 & 328, which are mistakenly labeled as 336 & 338, in Fig. 3B, para [23]),
the capacitor includes a first signal capacitor (comprising capacitor plates 322 & 324) and a second signal capacitor (comprising capacitor plates 326 & 328),
the signal transmitted through the capacitor includes a first signal (TX/RX 1 CH1) and a second signal (TX/RX 1 CH2),
the first signal (TX/RX 1 CH1) is transmitted from the first circuit toward the second circuit through the first signal capacitor (comprising capacitor plates 322 & 324), and
the second signal (TX/RX 1 CH2) is transmitted from the first circuit toward the second circuit through the second signal capacitor (comprising capacitor plates 326 & 328).
Allowable Subject Matter
3. Claims 3-8, 11, 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an insulating chip and a signal transmission device with all exclusive limitations as recited in claims 3, 11 and 18, which may be characterized (claim 3) in that a first electrode pad is arranged on the element insulation layer and electrically connected to the first electrode plate, and a second electrode pad is arranged on the element insulation layer and electrically connected to the second electrode plate, (claim 11) in that a distance between the first electrode plate and the second electrode plate in the first direction is greater than a distance between the first electrode plate and the substrate in the thickness-wise direction of the element insulation layer and is greater than a distance between the second electrode plate and the substrate in the thickness-wise direction of the element insulation layer, and (claim 18) in a first mount frame on which the first chip is mounted and a second mount frame on which the second chip is mounted, and in that the insulation chip is mounted on the first mount frame or the second mount frame via an insulation member.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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07-10-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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