DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12, 15-17 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the conductive patterns" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "a third impurity-doped region configured to penetrate the first impurity-doped region to electrically connect one of the both ends of the conductive sensing line to a first portion of the second impurity-doped region" in lines 19-23. It is unclear which conductive sensing line is being referenced in the limitation of the claim.
Claims 16-17 are rejected due to depending from claim 15.
Claim 21 recites the limitation "the second conductive sensing line" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 9-10, and 12-22 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Polomoff et al. (US 2021/0356514 A1; hereinafter “Polomoff”).
In regard to claim 1, Polomoff teaches a semiconductor device (an integrated circuit (IC) 102) (Fig. 6 and paragraph 29), comprising:
a semiconductor substrate (semiconductor substrate 104 and doped layers thereon annotated as SUB in annotated Fig. 9 below) comprising a first impurity-doped region (a p+-doped semiconductor located in the region annotated as sub functions as the first impurity-doped region in Fig. 9) (annotated Fig. 9 and paragraph 53);
a guard ring (a guard ring 110) formed over the semiconductor substrate (Fig. 9 and paragraph 30), the guard ring being electrically connected to the first impurity-doped region (the guard ring 110 may be coupled to the n-doped tunneling connection 332 using at least one p+-doped semiconductor interconnect 366) (Fig. 9 and paragraphs 48 and 53);
a crack detecting circuit (detection and monitoring circuit 126) formed over the semiconductor substrate (Fig. 6 and paragraph 32);
a conductive sensing line (independent and electrically conductive PLINE 320) disposed at a location isolated from the crack detecting circuit with the guard ring interposed between the conductive sensing line and the crack detecting circuit over the semiconductor substrate (the guard ring 110 is shown disposed between the independent and electrically conductive PLINE 320 which is isolated from the detection and monitoring circuit 126) (Fig. 6 and paragraph 42), the conductive sensing line being configured to extend along the guard ring and configured to have both ends (opposing ends 340) spaced apart from each other (the electrically conductive PLINE 320 is shown extending along the guard ring 110 and opposing ends 340 are shown spaced apart in Fig. 6) (Fig. 6 and paragraph 45);
a second impurity-doped region (n-doped tunneling connection 330 of one of the opposing ends 340) buried in the first impurity-doped region and extending under the guard ring (the n-doped tunneling connection 330 is shown under the guard ring 110 in Fig. 8) (Fig. 6, Fig. 8 and paragraph 42);
a third impurity-doped region (a doped region 356 of the semiconductor substrate 104) configured to penetrate the first impurity-doped region so that the third impurity-doped region electrically connects one of the ends of the conductive sensing line to a first portion of the second impurity-doped region (the electrically conductive PLINE 320 is shown in a p-doped portion 358 of the semiconductor substrate 104, the doping of the semiconductor region 356, the semiconductor interconnect 364, and the first portion annotated FP of the tunneling connection 330 of one of the opposing ends 340 allow the passage of an electrical signal when measuring the electrical characteristic of PLINE 320) (Fig. 9 and paragraph 48); and
a fourth impurity-doped region (the tunneling connection 330 of another one of the opposing ends 340) configured to penetrate the first impurity-doped region so that the fourth impurity-doped region electrically connects the crack detecting circuit to a second portion of the second impurity-doped region (opposing ends 340 of first PLINE 320 may be coupled via electrically conductive semiconductor tunneling connections 330 to the detection and monitoring circuit 126) (Fig. 8 and paragraph 45).
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In regard to claim 2, Polomoff teaches wherein the first impurity-doped region is doped with impurities having a conductive type different from a conductive type of the second impurity-doped region (the first impurity region is formed of p-type doped impurities while the second is formed of n-type impurities) (Fig. 9 and paragraph 53).
In regard to claim 3, Polomoff teaches wherein a portion of the first impurity-doped region (p+-doped semiconductor interconnect 366) is disposed between the second impurity-doped region and the guard ring and electrically isolates the second impurity-doped region and the guard ring (the reverse biased pn junctions formed between the p+ doped semiconductor interconnect 366 and the n-doped tunneling connection 330 electrically isolate the guard ring 110 from the n-doped tunneling connection 330) (Fig. 9 and paragraph 53).
In regard to claim 4, Polomoff teaches wherein:
the first impurity-doped region includes p-type conductive impurities (the p+ doped semiconductors located in the region annotated as SUB functions as the first impurity-doped region in Fig. 9) (annotated Fig. 9 and paragraph 53), and the second impurity-doped region includes n-type conductive impurities (n-doped tunneling connection 330 contains n-type impurities) (Fig. 9 and paragraph 53).
In regard to claim 5, Polomoff teaches wherein the third and fourth impurity-doped regions are each doped with impurities having a conductive type different from a conductive type of the first impurity-doped region (the doped region 356 and the tunneling connection 330 are both shown to be n-type) (Fig. 9 and paragraph 49).
In regard to claim 9, Polomoff teaches further comprising an insulating layer (a dielectric material 144) formed on a surface of the semiconductor substrate and configured to electrically isolate a portion of the first impurity-doped region and a portion of the third impurity-doped region (the top surfaces of the doped portion 358 of the semiconductor substrate 104 and the doped semiconductor region 356 would be covered and insulated by the dielectric material 144) (Fig. 8, Fig. 9 and paragraph 34).
In regard to claim 10, Polomoff teaches further comprising a first vertical connector (electrically conductive metal interconnects 362) configured to electrically connect the one end of the conductive sensing line and the third impurity-doped region (Fig. 8 and paragraph 47).
In regard to claim 12, Polomoff teaches wherein the conductive sensing line comprises:
first, second, and third stacks of the conductive patterns that are sequentially disposed (first metal sections 350 annotated FS, second metal sections 350 annotated SS, and third metal sections 350 annotated TS are shown in annotated Fig. 8 below) (Fig. 8 and paragraph 46);
a top connection pattern (a metal connector 354) configured to connect a first topmost conductive pattern of the first stack of the conductive patterns and a second topmost conductive pattern of the second stack of the conductive patterns (metal connector 354 is shown connecting top metal segments 360 of metal sections 350 annotated FS and SS in annotated Fig. 8 below) (Fig. 8 and paragraphs 46-47); and
a bottom connection pattern (metal connector 352) configured to connect a first bottommost conductive pattern of the second stack of the conductive patterns and a second bottommost conductive pattern of the third stack of the conductive patterns (metal connector 352 is shown connecting bottom metal segments 360 of metal sections 350 annotated SS and TS in annotated Fig. 8 below) (Fig. 8 and paragraph 46-47).
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In regard to claim 13, Polomoff teaches wherein the guard ring comprises a stack of the conductive patterns that is electrically connected to the first impurity-doped region and that is electrically grounded (the guard ring 110 is shown with conductive metal interconnects 362 and is grounded due to the reverse biased pn junctions formed between the p+-doped semiconductor interconnect(s) 366 and the n-doped tunneling connection 332) (Fig. 9 and paragraph 53).
In regard to claim 14, Polomoff teaches wherein the guard ring encloses a region comprising the crack detecting circuit by surrounding the region (the guard ring 110 is shown the detection and monitoring circuit 126 in Fig. 6).
In regard to claim 15, Polomoff teaches a semiconductor device (an integrated circuit (IC) 102) (Fig. 6 and paragraph 29), comprising:
a semiconductor substrate (semiconductor substrate 104 and doped layers thereon annotated as SUB in annotated Fig. 9 above) comprising a first impurity-doped region (a p+-doped semiconductor located in the region annotated as sub functions as the first impurity-doped region in Fig. 9) (annotated Fig. 9 and paragraph 53);
a guard ring (a crackstop 112) formed over the semiconductor substrate and is electrically connected to the first impurity-doped region (the crackstop 112 may be coupled to the n-doped tunneling connection 332 using at least one p+-doped semiconductor interconnect 366) (Fig. 9 and paragraphs 48 and 53);
a crack detecting circuit (detection and monitoring circuit 126) formed over the semiconductor substrate (Fig. 6 and paragraph 32);
a first conductive sensing line (independent and electrically conductive PLINE 322) disposed at a location isolated from the crack detecting circuit with the guard ring interposed between the conductive sensing line and the crack detecting circuit over the semiconductor substrate, configured to extend along the guard ring (the crackstop 112 is shown disposed between the independent and electrically conductive PLINE 322 which is isolated from the detection and monitoring circuit 126) (Fig. 6 and paragraph 42), and configured to have both ends spaced apart from each other (opposing ends 342 of second PLINE 322 are shown spaced apart in Fig. 6) (Fig. 6 and paragraph 45);
a second conductive sensing line (independent and electrically conductive PLINE 320) configured to extend along the guard ring between the guard ring and the crack detecting circuit over the semiconductor substrate and configured to have both ends spaced apart from each other (the electrically conductive PLINE 320 is shown extending along the crackstop 112 and opposing ends 340 are shown spaced apart in Fig. 6) (Fig. 6 and paragraph 45;
a second impurity-doped region (n-doped tunneling connection 332 of one of the opposing ends 342) buried in the first impurity-doped region and configured to extend to pass under the guard ring (the n-doped tunneling connection 332 is shown under the crackstop 112 in Fig. 6) (Fig. 6, and paragraph 45);
a third impurity-doped region (a doped region 356 of the semiconductor substrate 104) configured to penetrate the first impurity-doped region to electrically connect one of the both ends of the conductive sensing line to a first portion of the second impurity-doped region (the electrically conductive PLINE 320 is shown in a p-doped portion 358 of the semiconductor substrate 104, the doping of the semiconductor region 356, the semiconductor interconnect 364, and the first portion annotated FP of the tunneling connection 330 of one of the opposing ends 340 allows the passage of an electrical signal when measuring the electrical characteristic of PLINE 320) (Fig. 9 and paragraph 48); and
a fourth impurity-doped region (the tunneling connection 332 of another one of the opposing ends 342) configured to penetrate the first impurity-doped region to electrically connect the crack detecting circuit to a second portion of the second impurity-doped region (opposing ends 342 of electrically conductive PLINE 322 may be coupled via electrically conductive semiconductor tunneling connections 332 to the detection and monitoring circuit 126) (Fig. 8 and paragraph 45).
In regard to claim 16, Polomoff teaches further comprising a conductive pattern (metal connectors 352 and 354) formed over the semiconductor substrate connecting the second conductive sensing line to the crack detecting circuit (opposing ends 340 of first PLINE 320 may be coupled via electrically conductive semiconductor tunneling connections 330 to the detection and monitoring circuit 126) (Fig. 6 and paragraph 45), wherein the second conductive sensing line is electrically isolated from the first and second impurity-doped regions (as each PLINE forms independent connections the PLINE 320 would be electrically isolated from the first and second impurity-doped regions associated with PLINE 322) (Fig. 6 and paragraph 42).
In regard to claim 17, Polomoff teaches wherein the first impurity-doped region is doped with impurities having a conductive type different from a conductive type of the second impurity-doped region (the first impurity region is formed of p-type doped impurities while the second is formed of n-type) (Fig. 9 and paragraph 53)
In regard to claim 18, Polomoff teaches a semiconductor device (an integrated circuit (IC) 102) (Fig. 6 and paragraph 29), comprising: a semiconductor substrate (semiconductor substrate 104 and doped layers thereon annotated as SUB in annotated Fig. 9 above) comprising a first impurity-doped region (a p+doped semiconductor located in the region annotated as sub functions as the first impurity-doped region in Fig. 9) (annotated Fig. 9 and paragraph 53);
first and second guard rings (a crackstop 112 and crackstop 114 respectively) formed over the semiconductor substrate and electrically connected to the first impurity-doped region (the crackstop 112 and crackstop 114 may be coupled to the n-doped tunneling connection 332 using at least one p+-doped semiconductor interconnect 366) (Fig. 9 and paragraphs 48 and 53);
a crack detecting circuit (detection and monitoring circuit 126) formed over the semiconductor substrate (Fig. 6 and paragraph 32);
a first conductive sensing line (second conductive PLINE 322) isolated from the crack detecting circuit with the first guard ring interposed between the first conductive sensing line and the crack detecting circuit over the semiconductor substrate (the crackstop 112 is shown disposed between the PLINE 322 which is isolated from the detection and monitoring circuit 126) (Fig. 6 and paragraph 42), disposed between the first and second guard rings (the second conductive PLINE 322 is shown disposed between the crackstop 112 and crackstop 114 in Fig. 6), configured to extend along the first guard ring, and configured to have both ends spaced apart from each other (second PLINE 322 is shown extending along the crackstop 112 and opposing ends 342 of second PLINE 322 are shown spaced apart in Fig. 6) (Fig. 6 and paragraph 45);
a second impurity-doped region (n-doped tunneling connection 332 of one of the opposing ends 342) buried in the first impurity-doped region and configured to extend to pass under the guard ring (the n-doped tunneling connection 332 is shown under the crackstop 112 in Fig. 6) (Fig. 6, and paragraph 45);
a third impurity-doped region (a doped region 356 of the semiconductor substrate 104) configured to penetrate the first impurity-doped region and electrically connect one of the both ends of the first conductive sensing line to a first portion of the second impurity-doped region (the electrically conductive PLINE 320 is shown in a p-doped portion 358 of the semiconductor substrate 104, the doping of the semiconductor region 356, the semiconductor interconnect 364, and the first portion annotated FP of the tunneling connection 330 of one of the opposing ends 340 allows the passage of an electrical signal when measuring the electrical characteristic of PLINE 320) (Fig. 9 and paragraph 48); and
a fourth impurity-doped region (the tunneling connection 332 of another one of the opposing ends 342) configured to penetrate the first impurity-doped region and electrically connect the crack detecting circuit to a second portion of the second impurity-doped region (opposing ends 342 of electrically conductive PLINE 322 may be coupled via electrically conductive semiconductor tunneling connections 332 to the detection and monitoring circuit 126) (Fig. 8 and paragraph 45).
In regard to claim 19, Polomoff teaches further comprising a second conductive sensing line configured to extend along the first guard ring between the first guard ring and the crack detecting circuit over the semiconductor substrate and configured to have both ends spaced apart from each other (the electrically conductive PLINE 320 is shown extending along the crackstop 112 and opposing ends 340 are shown spaced apart in Fig. 6) (Fig. 6 and paragraph 45).
In regard to claim 20, Polomoff teaches further comprising a conductive pattern (metal connectors 352 and 354) formed over the semiconductor substrate so that the conductive pattern connects the second conductive sensing line to the crack detecting circuit (opposing ends 340 of first PLINE 320 may be coupled via electrically conductive semiconductor tunneling connections 330 to the detection and monitoring circuit 126) (Fig. 6 and paragraphs 45), wherein the second conductive sensing line is electrically isolated from the first and second impurity-doped regions (as each PLINE forms independent connections the PLINE 320 would be electrically isolated from the first and second impurity-doped regions associated with PLINE 322) (Fig. 6 and paragraph 42).
In regard to claim 21, Polomoff teaches wherein the second conductive sensing line is disposed to not overlap with the second impurity-doped region (the electrically conductive PLINE 320 is shown not overlapping the n-doped tunneling connection 332 of one of the opposing ends 342 in Fig. 6).
In regard to claim 22, Polomoff teaches wherein the first impurity-doped region is doped with impurities having a conductive type different from a conductive type of the second impurity-doped region (the first impurity region is formed of p-type doped impurities while the second is formed of n-type) (Fig. 9 and paragraph 53).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Polomoff as applied to claim 1 above.
In regard to claim 11, Polomoff teaches further comprising a second vertical connector configured to electrically connect the crack detecting circuit and the fourth impurity-doped region (connections may be provided over and/or under one or more of the guard ring 110, crackstop 112, and crackstop 114 to couple PLINEs to the detection and monitoring circuit 126, the examiner takes official notice that a second vertical connection exists that would connect the tunneling connection 330 of another one of the opposing ends 340 to the detection and monitoring circuit 126) (paragraph 31).
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to claim 6, Polomoff is considered the closes prior art of reference. However Polomoff fails to teach “the third and fourth impurity-doped regions each have a higher impurity doping concentration than the second impurity-doped region.” Polomoff is silent regarding doping concentrations within the device.
In regard to claim 7, Polomoff is considered the closes prior art of reference. However Polomoff fails to teach “wherein: the first portion of the second impurity-doped region overlaps with the third impurity-doped region, the second portion of the second impurity-doped region overlaps with the fourth impurity-doped region, and the second impurity-doped region further comprises a third portion that connects the first portion and the second portion and that overlaps with the guard ring”. Polomoff does not teach overlapping impurity regions that match the layout as described.
In regard to claim 8, Polomoff fails to teach “a fifth impurity-doped region disposed within a portion of the first impurity-doped region, which is disposed between the second impurity-doped region and the guard ring and has a higher impurity doping concentration than the first impurity-doped region”. Polomoff is silent regarding doping concentrations within the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US 2022/0293532 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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