Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant's arguments filed 1/13/2026 have been fully considered but they are not persuasive.
The Remarks do not address the teachings of Gabryjelski, paragraph 3, which are provided below for convenience.
[0003] In certain computing systems, when a server experiences a system error, a processor of the server can instruct a corresponding memory controller to flush a buffer and write any data still in the buffer to an operatively coupled NVDIMM. The memory controller can then command the NVDIMMs to switch to self-refresh mode before the server provides a signal (e.g., a voltage signal) to an input pin (e.g., the SAVE# pin) on the NVDIMM to initiate data persistence in the NVDIMMs. In response to the provided signal, the NVDIMM can then copy and persistently store all data from the DRAM module to the corresponding flash memory module before power is removed from the NVDIMMs.
The Examiner maintains that the above cited portions of Paragraph 3, in addition to the other citations of Gabryjelski teach all of the limitations of the independent claims.
The above highlighted section of paragraph 3 teaches the scope of the independent claims. The memory controller instructs the memory device to switch to self-refresh mode, and the server by way of the BMC provides a signal to input pin (see paragraph 41; SAVE# pin), to initiate data persistence in the memory device. The data persistence requires the memory device to copy and persistently store all the data from the volatile memory to the non-volatile storage module. This process can only be done by exiting a self-refresh mode where a memory module generates its own refresh cycles to maintain data during sleep or other low power states.
- The amendments directed at overcoming the 112 rejection has been acknowledged and the 112 rejection has been withdrawn.
- The objection to the specification has not been addressed and is repeated below.
Specification
The disclosure is objected to because of the following informalities: Paragraph 29, line 20, recites, “command decoding circuit 123”. However, the Drawings show reference numeral 120-2 for the command decoding circuit. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gabryjelski, U.S. PGPUB No. 2017/0322740.
Per Claim 1, Gabryjelski discloses a memory system comprising:
a memory device (Paragraph 38, Fig. 2A; Hybrid Memory Device 120);
a controller configured to control the memory device through an in-band interface (Paragraph 71, Figure 4A; Memory controller 114 and bus 109);
and a baseboard management controller configured to control the memory device through a side-band interface (Paragraphs 37 and 41, Figures 2-4; BMC 132 and input pin 127),
wherein the memory device is configured to enter a self-refresh mode based on in-band signals that are received through the in-band interface (Paragraphs 3 highlights that the memory controller can command the memory to switch to a self-refresh mode.)
and to terminate the self-refresh mode based on side-band signals that are received through the side-band interface (Paragraphs 3 further teaches providing a signal on SAVE# pin 127 to initiate data persistence, which would require an exit from self-refresh mode of the volatile memory in order to write data from the volatile memory to the non-volatile memory, as detailed in paragraphs 41, 49, 54, and 71).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Gabryjelski, U.S. PGPUB No. 2017/0322740 in view of Setheraman et al. U.S. PGPUB No. 2023/0385208.
Per Claim 2, Gabryjelski does not elaborate on the specific signals present on the bus 109.
However, Setheraman similarly teaches a memory controller 114/1020 in communication with a memory device 120/1070, and further teaches the data connection between said components is an in-band bus (Paragraph 31) comprising an external chip selection signal, an external clock, and an external command address signal (Paragraph 131, Figure 10).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the in-band bus of Gabryjelski to comprise the signals as taught by Setheraman, because chip select signals are needed for selecting DRAM modules (Gabryjelski; Paragraph 39), and clock and command/address signals are necessary for indicating a read/write command and clocking the read or write of data from/to the memory device (per the policies of Gabryjelski; Paragraphs 55, 56).
Per Claim 3, Setheraman further teaches the memory device generating, as a setting signal, setting information that has been stored in a mode register set based on the side-band signals (Paragraph 81, mode register writes; Paragraph 40, registers 222 can include DFE and termination settings.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize registers within the memory device, as taught by Setheraman, within the memory device of Gabryjelski, because the module controller 126 of Gabryjelski is configured to monitor, read, write, erase, and perform other suitable operations on memory devices 122 and 124, and a register is a common storage apparatus for saving information such as settings.
Per Claim 4, Gabryjelski discloses the memory system of claim 3, wherein the memory device controls at least one internal circuit to be on based on the setting signal and enables an operation of setting the internal circuit to be performed based on the setting signal (Paragraphs 41, 49, 54, and 71; BMC can command the non-volatile memory 124 to selectively persist certain data contained in the volatile memory module 122 in response by way of a signal on input pin 127. This persistence operation exits the memory from a self-refresh mode and is considered turning the memory “on”. The memory devices 122/124 within memory device 120 can be considered internal circuits.).
Per Claim 5, Gabryjelski discloses the memory system of claim 3, wherein the memory device comprises an internal circuit configured to disable a self-refresh signal that has been enabled based on the setting signal (Paragraphs 41, 49, 54, and 71; BMC can command the non-volatile memory 124 to selectively persist certain data contained in the volatile memory module 122 in response by way of a signal on input pin 127. This persistence operation exits the memory from a self-refresh mode. The memory devices 122/124 within memory device 120 can be considered internal circuits.).
Per Claim 12, Gabryjelski discloses an operating method of a memory device (Paragraph 38, Fig. 2A; Hybrid Memory Device 120), the operating method comprising: entering a standby state based on in-band signals that are received through an in-band interface (Paragraphs 3, 35, and 71, Figure 4A; Memory controller 114 and bus 109 can command the memory to switch to a self-refresh mode, which is a standby state.); generating a setting command by decoding side-band signals that are received through a side-band interface (Paragraphs 3, 37 and 41, Figures 2-4; BMC 132 an input pin 127); outputting setting information based on the setting command; and switching from the standby state to an active state based on the setting information (Paragraphs 3 further teaches providing a signal on SAVE# pin 127 to initiate data persistence, which would require an exit from self-refresh mode of the volatile memory in order to write data from the volatile memory to the non-volatile memory, as detailed in paragraphs 41, 49, 54, and 71).
Gabryjelski does not specifically disclose a register set.
However, Setheraman teaches the memory device transmitting, as a setting signal, setting information that has been stored in a mode register set based on the side-band signals (Paragraph 81, mode register writes; Paragraph 40, registers 222 can include DFE and termination settings.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize registers within the memory device, as taught by Setheraman, within the memory device of Gabryjelski, because the module controller 126 of Gabryjelski is configured to monitor, read, write, erase, and perform other suitable operations on memory devices 122 and 124, and a register is a common storage apparatus for saving information such as settings.
Allowable Subject Matter
Claims 6-11 and 15-17 are allowed.
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is considered to distinguish over Gabryjelski and the prior art due to the specific memory device circuits that are claimed and the generation of the normal command and setting signal and the operation of the internal circuit of the memory device according to the normal command and setting signal.
Claim 15 is considered to distinguish over Gabryjelski and the prior art due to the activation and deactivation of the memory device reception circuit for in-band communication according to the self-refresh termination command received on the side-band interface.
Gabryjelski is considered to be the closest prior art to claims 6 and 15 for reasons outlined above in the rejection.
Additionally, U.S. PGPUB No. 2019/0392886 discloses ODT circuitry 146 but the ODT is performed while the memory device 140 is in a low power state (Paragraph 47), and not upon switching from a standby state to an active state as claimed.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Brian T Misiura/
Primary Examiner, Art Unit 2175