DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pothukuchi et al. (USPGPub No. 2022/0085001, from hereinafter “Pothukchi”).
Regarding claim 11, Pothukuchi teaches a semiconductor package comprising:
a redistribution layer (Fig. 4A-4B, 405; see Fig. 1, redistribution of interconnects 115) on a substrate (Fig. 4A-B, 471);
a semiconductor chip (Fig. 4A, 410 and Paragraph 40) on the redistribution layer;
a first stack structure (Fig. 4A, stacked portions 421-426 on the left side of 405) on the redistribution layer and spaced apart from the semiconductor chip in a first horizontal direction; and
a plurality of first optical fibers (Figs. 4A-4B, 422; Fig. 1B, 122 and Paragraph 26) coupled to the first stack structure, wherein the first stack structure includes a plurality of optical integrated circuit chips (Fig. 4A-4B, 420; Paragraph 26) stacked vertically with respect to each other, and each of the first optical fibers is spaced apart from another in a vertical direction (e.g. in Fig. 4A along line B-B’).
Regarding claim 15, Pothukuchi teaches a second stack structure (see Fig. 3, there are two stack structures 322 adjacent to each other on each side of 305) adjacent to the first stack structure in a second horizontal direction intersecting with the first horizontal direction, and a plurality of second optical fibers coupled to the second stack structure.
Regarding claim 16, Pothukuchi teaches that the first optical fibers (Figs. 4A-4B, 422) are spaced apart from the second optical fibers in the second horizontal direction (Fig. 3, i.e. along the edge of redistribution layer 405), respectively, and the second optical fibers are spaced apart from each other in the vertical direction (i.e. in Fig. 4A along line B-B’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi in view of Patel et al. (US Patent No. 9,995,881, from hereinafter “Patel”).
Regarding claim 14, Pothukuchi does not teach a connection terminal interposed between and connected to a lowermost optical integrated circuit chip, among the plurality of optical integrated circuit chips, and the redistribution layer and connected to each other, wherein the connection terminal includes a solder bump.
Patel teaches a connection terminal interposed between and connected to a lowermost optical integrated circuit chip (Fig. 1, 140), and a redistribution layer (Fig. 1, 120) and connected to each other, wherein the connection terminal includes a solder bump (Fig. 1, 115 and Col 3 Ln 62-66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a solder bump between the lower most optical integrated circuit chip and redistribution layer of Pothukuchi as taught by Patel in order to achieve the predictable result of electrically connecting the optical integrated circuit chip and redistribution layer.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pothukuchi, in view of Vegny et al. (USPGPub No. 2003/0002801, from hereinafter “Vegny”).
Regarding claim 17, Pothukuchi does not teach that the first optical fibers and the second optical fibers are connected to one bracket.
Vegny teaches that a plurality of optical fibers (Fig. 1, 9) that connected to one bracket (Fig. 1, 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bracket connecting the first and second optical fibers of Pothukuchi as taught by Vegny in order to align the plurality of optical fibers simultaneously (Paragraph 25).
Allowable Subject Matter
Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1-10 and 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest
in claim 1:
wherein the stack structure includes a first optical integrated circuit chip and a second optical integrated circuit chip on the first optical integrated circuit chip, wherein each of the first optical integrated circuit chip and the second optical integrated circuit chip includes a first region and a second region, among the first region and the second region, the first region is relatively adjacent to the semiconductor chip and the second region is relatively adjacent to an outer portion of the substrate, and
the first optical integrated circuit chip defines a first notch and a first groove in the second region, the first notch recessed upwards in a vertical direction from a lower surface of the first optical integrated circuit chip, the first groove recessed downwards in the vertical direction from an upper surface of the first optical integrated circuit chip.
in claim 18:
the first optical integrated circuit chip comprises, a first body including an optical integrated circuit and an electronic integrated circuit, a first upper pad on an upper surface of the first body and a first lower pad on a lower surface of the first body, a through via penetrating the first body and connected to the first upper pad and the first lower pad, and
the first optical integrated circuit chip defining a first notch and a first groove in the second region, the first notch recessed upwards in a vertical direction from a lower surface of the first optical integrated circuit chip, the first groove recessed downwards in the vertical direction from an upper surface of the first optical integrated circuit chip.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
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