DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 10 is objected to because of the following informalities: claim 10 recites: “the second package element” which lacks an antecedent basis. For examination purposes, dependency of claim 10 (“claim 1”) is interpreted to be “claim 9” which provides said antecedent basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1 and 4-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leong et al. U.S. Patent Application Publication 2021/0120679 A1 (the ‘679 reference).
The reference discloses in Figs. 1 through and particularly 4, and related text a combination-type semiconductor package as claimed.
Referring to claim 1, the ‘679 reference discloses a combination-type semiconductor package comprising:
a wiring plate comprising a package substrate or an interposer substrate (printed circuit substrate 12, interposing between electrical device 10 to a larger printed circuit board, para [36] (paragraph(s) [0036])), meeting the claim limitation “at least one of a package substrate, a redistribution structure, and an interposer substrate”;
a package element (16/34/40/36, para [36, 38, 40]) mounted on the wiring plate (12);
a delamination-preventing layer (phosphorate-based layer 42, para [41, 69]) covering the package element (16/34/40/36); and
a package molding layer (38, para [39]) configured to encapsulate the package element (16/34/40/36) and the delamination-preventing layer (42) on the wiring plate (12),
wherein the delamination-preventing layer (42) prevents delamination between the package element (16/34/40/36) and the package molding layer (38) (para [71]: “…stronger bonding provided by the first adhesion layer 40 may reduce, or substantially eliminate, the formation of voids and delamination between the undercoating layer 36 and the plurality of chip capacitors 16 and the substrate 12. Similarly, is it believed that the second adhesion layer 42 formed at block 408 bonds strongly with the undercoating layer 36 and the plurality of chip capacitors 16 and with the top coating layer 38 to tie the top coating layer 38 to the undercoating layer 36. The stronger bonding and improved adhesion provided by the second adhesion layer 42 reduce, or substantially eliminate, the formation of voids between the top coating layer 38 and the undercoating layer 36, and between the top coating layer 38 and the plurality of chip capacitors 16”).
Referring to claim 4, the reference further discloses that the delamination-preventing layer (42) comprises an adhesive layer (42) that bonds the package element (16/34/40/36) and the package molding layer (38) to each other, and the adhesive layer comprises polymer (phosphorate-based layer, para [41, 69]).
Referring to claim 5, Fig. 4 depicts that the delamination-preventing layer (42) has a corrugated outer surface.
Referring to claim 6, the reference further discloses that the package element (16/34/40/36) is a first package element and the combination-type semiconductor package comprises a second package element (another package element 16/34/40/36 or integrated circuit die 14, para [35]), the first package element and the second package element each being mounted on the wiring plate (12) and horizontally spaced apart from each other, and wherein the delamination-preventing layer (42) covers at least one of the first package element and the second package element.
Allowable Subject Matter
4. Claims 11-20 are allowable over the prior art of record.
Claims 2-3 and 7-10, insofar as in compliance with the claim objections detailed above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a combination-type semiconductor package with all exclusive limitations as recited in claims 2-3, 7-9, 11 and 18, which may be characterized (2) in that the package element comprises a semiconductor chip, (claim 3) the package element comprises a semiconductor package that comprises a chip body, (claims 7 and 8) the first package element comprises a first semiconductor chip, (claim 9) in that the first package element and the second package element each being mounted on the wiring plate and vertically spaced apart from each other, (claim 11) the second package element comprises a semiconductor package that comprises a second semiconductor chip comprising a second chip body and a body molding layer, and in that a delamination-preventing layer covers the body molding layer of the second package element, and (claim 18) the first package element comprises a first semiconductor chip, the second package element comprises a second semiconductor chip, and in that a delamination-preventing layer covers at least one of the first package element and the second package element.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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07-14-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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