Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicant’s remarks, see Rejections Under 35 U.S.C. §112(b) (page 10 of 13), filed June 3, 2026, with respect to claims 1-13 and 21 have been fully considered and are persuasive. The §112(b) rejections of April 9, 2026 have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to independent claim 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Elend et al. (US 12438746 B2); hereinafter Elend.
Regarding Claim 14, Elend discloses a method [Abstract; Fig. 1/2] comprising: detecting [Abstract], by an arbitration detection circuit [inside 228, as 228 performs a loss arbitration; column 14, lines 34-35] of a communication transceiver [208], a transmission arbitration status of the communication transceiver [column 14, lines 29-46]; and responsive to the transmission arbitration status being an arbitration loss, causing, by the arbitration detection circuit, communication operation of the communication transceiver to be disabled [column 14, lines 29-46].
Regarding Claim 15, Elend discloses the method of claim 14, wherein detecting the arbitration status includes determining that the arbitration loss has occurred responsive to a mismatch in values between a transmit data input signal and a receive data output signal [column 14, lines 29-46].
Allowable Subject Matter
Claims 1-13 and 21 are allowed.
Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Referring to Claim 1, Jang (US 20240089146 A1), hereinafter Jang, discloses a circuit [Fig. 2], comprising: a first transistor [T2] having a control terminal and first and second terminals; a second transistor [T1] having a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor; a first resistor [R1] having first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor; a digital logic circuit [431] having an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal [+ of 431] of the digital logic circuit coupled to a data transmit input terminal [H] of the circuit, and the second input terminal [- of 431] of the digital logic circuit coupled to a data receive output terminal [P coupled through Rx of 414] of the circuit.
However, Jang does not disclose nor render obvious wherein the digital logic circuit is configured to: responsive to detecting an arbitration loss associated with a controller area network (CAN) communication, determine whether to: turn off the second transistor; and precharge the first terminal of the second transistor, as cited with the rest of the claimed limitation.
Further, the prior art overall does not teach or make obvious the limitation described above in consideration of the claim overall. Thus, claim 1 is novel and allowed. Dependent claims of claim 1 are also allowed.
Referring to Claim 10, Jang discloses a circuit [Fig. 2], comprising: a first transistor [T2] having a control terminal and first and second terminals; a second transistor [T1] having a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor; a first resistor [R1] having first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor; a digital logic circuit [431] having an output coupled to the control terminal of the second transistor.
Jang does not explicitly disclose wherein the digital logic circuit configured to: responsive to detecting an arbitration loss, provide a gate control signal having a logic high value to the control terminal of the second transistor; responsive to not detecting an arbitration loss, or to detecting an arbitration win, provide the gate control signal having a logic low value to the control terminal of the second transistor; a pull-up circuit configured to, responsive to the gate control signal having the logic low value, pull up the first terminal of the first transistor to a supply voltage to precharge the first terminal of the second transistor; and a pull-down circuit configured to, responsive to the gate control signal having the logic high value, pull down the control terminal of the second transistor to a specified voltage.
However, Korolev et al. (US 20190140644 A1), hereinafter Korolev, discloses a circuit [Fig. 2/5], comprising: a digital logic circuit [202] having an output [Y]; a pull-up circuit [204] configured to, responsive to the gate control signal having the logic low value [paragraph 0012/0030], pull up the first terminal of the first transistor to a supply voltage [Vdd; paragraph 0024] to precharge the first terminal of the second transistor; and a pull-down circuit [206] configured to, responsive to the gate control signal having the logic high value [paragraph 0012/0031], pull down the control terminal of the second transistor to a specified voltage [Vss; paragraph 0024].
However, Jang, in view of Korolev, does not disclose nor render obvious wherein the digital logic circuit configured to: responsive to detecting an arbitration loss, provide a gate control signal having a logic high value to the control terminal of the second transistor; responsive to not detecting an arbitration loss, or to detecting an arbitration win, provide the gate control signal having a logic low value to the control terminal of the second transistor, as cited with the rest of the claimed limitation.
Further, the prior art overall does not teach or make obvious the limitation described above in consideration of the claim overall. Thus, claim 10 is novel and allowed. Dependent claims of claim 10 are also allowed.
Referring to Claim 16, the prior art of the record does not disclose nor render obvious wherein the communication transceiver includes an arbitration detection logic circuit configured to detect the transmission arbitration status of the communication transceiver, the arbitration detection logic circuit comprising: an exclusive OR (XOR) logic circuit having an output terminal and first and second input terminals; a resistor having first and second terminals, the first terminal of the resistor coupled to the output terminal of the XOR logic circuit; a capacitor having first and second terminals, the first terminal of the resistor coupled to the second terminal of the resistor, and the second terminal of the capacitor coupled to a ground terminal; a transistor having a control terminal and first and second terminals, the first terminal of the transistor coupled to the second terminal of the resistor, and the second terminal of the transistor coupled to the ground terminal; a Schmitt trigger having input and output terminals, the input terminal of the Schmitt trigger coupled to the second terminal of the resistor; an AND logic circuit having an output terminal and first and second input terminals, the first input terminal of the AND logic circuit coupled to the output terminal of the XOR logic circuit, and the second input terminal of the AND logic circuit coupled to the output terminal of the Schmitt trigger; and a flip-flop having a data input terminal, a clock input terminal, a set input terminal, and a data output terminal, the clock input terminal coupled to the output terminal of the AND logic circuit, and the data output terminal coupled to the control terminal of the second transistor, as cited with the rest of the claimed limitation. Dependent claims of claim 16 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Adamson et al. (US 10922264 B1) and van Dijk et al. (US 20240168090 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571)272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571) 270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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