DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, and 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hampel et al. (US 2022/0247360 A1).
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Fig. 1 of Hampel reproduced for ease of reference.
Regarding claims 1 and 25, Hampel discloses (i.e. in Figs. 1, 9, 14-16, 25 and 32) a wideband Doherty Power Amplifier (DPA) circuit, (Fig. 1, Fig. 9, Fig. 32; §0004, lines 2–11; §0005, lines 10–25; §0099, lines 1–12; §0105, lines 1–4).
A main PA and an auxiliary PA (DM, DP1, DP2; Fig. 1, Fig. 14, Fig. 32; §0100, lines 1–12; §0108, lines 1–5).
An input power splitter configured to split an input power into the main PA and the auxiliary PA (ET; Fig. 1, Fig. 14, Fig. 32; §0002, lines 7–16; §0136, lines 1–12; §0137, lines 1–12).
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Fig. 9 (left) and Fig. 14 (right) of Hampel reproduced for ease of reference.
A multi-phasing block component to provide a phase difference between the main PA and the auxiliary PA (ET / DSP / Steering Function; Fig. 1, Fig. 14, Fig. 32; §0005, lines 24–33; §0136, lines 8–18).
A parasitic compensator & impedance inverter connected to the main PA to compensate a parasitic load P1 on the main PA and modulate an overall load on the DPA (LAH, AN1, ABN; Fig. 1, Fig. 15, Fig. 25, Fig. 32; §0101, lines 1–18; §0122, lines 1–8; §0153–§154).
A parasitic canceller connected to the auxiliary PA to compensate the parasitic load P2 on the auxiliary PA and avoid leakage of current from the main PA to the auxiliary PA, when the auxiliary PA is in an 'OFF' state (LAH, AN2; Fig. 1, Fig. 9, Fig. 15, Fig. 32; §0123, lines 1–10 §a); §0124, lines 1–12).
An output impedance transformer connected to the main PA and the auxiliary PA (C, ANI, W1, R1, R2; Fig. 1, Fig. 15, Fig. 16, Fig. 32; §0099, lines 10–18; §0119, lines 8–18).
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Fig. 15 of Hampel reproduced for ease of reference.
Thus, each specified limitation of Claim 1 is explicitly taught in US 2022/0247360 A1 to Hampel et al. A rejection under 35 U.S.C. 102 for anticipation is established.
Wherein per claim 9, Hampel also teaches that the multi-phasing block component is configured with a combination of delay lines to provide multiple phase shifts corresponding to different values of a frequency of operation to compensate a phase difference between the main PA and the auxiliary PA (FIG. 1, FIG. 15, FIG. 32, paragraphs §0005 , §0011 , §0101 , §0136 -§0137 ; describing digital control/input phase balancing component ET and λ/2, λ/4 delay transmission lines providing frequency-dependent phase adjustments between DM and DP1/DP2 .
Regarding claim 10, Hampel further teaches that the operation of the auxiliary PA is triggered when an output voltage of the main PA is more than a predefined peak voltage (FIG. 1, FIG. 7, paragraphs §0007 , §0099 -§0100 ; peak/auxiliary PA (DP1/DP2) turns ON when main PA (DM) reaches saturation/back-off voltage threshold).
And Per Claim 11, Hampel also teaches that an output current generated during the operation of the auxiliary PA causes modulation of the load on the main PA such that the load on the main PA reduces with increase in the input power (FIG. 7, paragraphs §0007 , §0099 ; current injected by auxiliary PA causes effective load impedance presented to main PA to decrease as input power increases).
Further per Claim 12, Hampel also teaches that each of the main PA and the auxiliary PA further comprise an input matching network (FIG. 1, FIG. 32, element AN1 (main PA input matching) and AN2 (auxiliary PA input matching), §0033).
And per Claim 13, Hampel teaches that each of the main PA and the auxiliary PA further comprise a broadband input power divider (FIG. 1, FIG. 14, FIG. 32, element ET / DPS, paragraphs §0014, §0136 -§0137; broadband digital signal divider ET driving inputs of main PA and auxiliary PAs).
R0140;ng claim 14, Hampel teaches that network parameters of the circuit are obtained simultaneously over the wide bandwidth, while considering their effect on each other and the effect of load impedance ZL provided by the output impedance transformer (FIG. 9, FIG. 31, equations (1)-(17), paragraphs §0105 -§0121 , §0139 -§0140 ; ABCD matrix chain calculation solving parameters Z0, Z1, ZE0 to ZE5 simultaneously considering mutual interactions over wide bandwidth).
And per claim 15, Hampel finally teaches that the Doherty Power Amplifier circuit is configured to modify the load to the transistor in the main PA over a wide input drive and wide bandwidth while avoiding clipping and corresponding addition of nonlinearity in operation of the DPA (FIG. 3, FIG. 11, FIG. 13, FIG. 23, paragraphs §0098 -§0100 , §0141 -§0150 ; load modulation architecture designed to optimize linearity, prevent excessive gain compression/clipping, and prevent breakdown non-linearities across broadband L-band drive levels).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hampel.
Regarding claim 2, Hampel teaches all limitations of claim 1, and further teaches Parasitic compensator/multi-harmonic transformation line LAH attached to main PA, DM (Fig. 1, Fig. 15, Fig. 32).
wherein the parasitic compensator & impedance inverter is designed based on parasitic load P1 of transistor Q1 connected to the main PA (Fig. 24, Fig. 25, Fig. 31, paragraphs §0101, §0122, §0151-§0156; explaining offset line LAH and absorption network ABN absorbing drain parasites C0, C1, L of the main amplifier transistor);
an impedance ZL provided by the output impedance transformer (Fig. 1, Fig. 15, Fig. 32, paragraphs §0099, §0119; output combiner C/AN output transformer providing a 50W load impedance RL).
and a quasi-open circuit impedance provided by the parasitic canceller, (Fig. 9, Fig. 31, paragraph §0124; offset line LAH of peak PAs DP1/DP2 transforms residual capacitance into an open circuit when auxiliary PA is OFF).
such that the parasitic compensator & impedance inverter provides a required load modulation over a large variation in the input power and wide bandwidth, (Fig. 3, Fig. 9, Fig. 11, Fig. 13, paragraphs §0099 -§0104, §0118 -§0123; multi-harmonic transformation line LAH and load matched combiner provide active load modulation over wide input drive and bandwidth); and
Hampel is silent about the parasitic compensator & impedance inverter configured with a plurality of sections, wherein each section comprising a transmission line and a shunt admittance.
However, Structuring an RF impedance inverter/matching network into a plurality of cascaded sections, where each section comprises a transmission line and a shunt admittance (discrete/stub capacitor/inductor), is a standard, ubiquitous technique in RF engineering used to widen transformation bandwidth (stepped-impedance/multi-section low-pass matching networks).
It would have been obvious to a Person Having Ordinary Skill in Art (PHOSA) prior to the effective filing date to implement Hampel's impedance inverter and parasitic compensator network (LAH/LMC) using a multi-section ladder configuration consisting of transmission line sections and shunt admittances.
The motivation for using multiple cascaded sections of transmission lines and shunt admittances is to achieve broader impedance matching bandwidth and finer control over higher-order harmonic terminations, as well-known in multi-section RF filter and matching network design.
Regarding claim 3, Hampel teaches all limitations of claim 2 (Fig. 15, Fig. 25, Fig. 32).
Hampel is silent about the number of sections in the parasitic compensator & impedance inverter is determined based on frequency of operation of the circuit, optimum load for the transistor and corresponding parasitic of the transistor.
Selecting the exact number of filter/matching sections based on operating frequency, target optimum load impedance, and transistor parasitic values is standard synthesis procedure for broadband matching networks in RF circuit design.
It would have been obvious to a PHOSA to select and calculate the specific number of sections in Hampel's multi-section parasitic compensator network based on the operating frequency band (e.g., L-band), the optimum load of the power transistor, and its measured parasitic elements.
Selecting the section count according to operating frequency and transistor parasitics allows the designer to achieve a targeted fractional bandwidth while maintaining physical size constraints and minimizing insertion loss.
Regarding claim 4, Hampel further teaches that the parasitic canceller provides cancellation of the parasitic load P2 presented by a transistor Q2 in the auxiliary PA based on the parasitic load P1 presented by the transistor Q1 on the main PA, (FIG. 9, FIG. 24, FIG. 25, FIG. 31, paragraphs §0105 -§0124 ; peak PAs DP1/DP2 include LAH/ABN networks designed to absorb parasites Pp1, Pp2 based on main PA parasites Pm and maintain open-circuit condition);
Hampel, however, is silent about the parasitic canceller configured with a plurality of sections, each section comprising a transmission line and a shunt admittance.
Implementing parasitic compensation/offset lines as a multi-section network (cascaded transmission lines and shunt admittances) is standard practice for extending offset line cancellation bandwidth.
It would have been obvious to a PHOSA to configure Hampel's auxiliary PA parasitic canceller (LAH line/ABN network at DP1/DP2) using a plurality of sections, each containing a transmission line and a shunt admittance.
Multi-section structuring provides wider bandwidth cancellation of auxiliary PA drain parasites across wide frequency ranges.
Regarding claim 5, Hampel teaches all limitations of claim 4, Hampel, however, is not explicit about number of sections in the parasitic canceller is determined based on frequency of operation of the circuit, optimum load for the transistor and corresponding parasitic loads P1, P2 of the transistors Q1, Q2, respectively.
However, determining the specific number of sections for an auxiliary PA parasitic compensation network based on operating frequency and the respective parasitics of the main and auxiliary transistors is conventional RF matching network optimization.
It would have been obvious to PHOSA to adjust the number of sections in Hampel's auxiliary PA parasitic canceller based on operating frequency and transistor parasitic values (P1, P2).
To optimize parasitic cancellation, minimize signal leakage into the OFF-state auxiliary PA, and maintain broadband Doherty load modulation.
Regarding claim 6, Hampel further teaches that the transmission line on each of the plurality of sections has a characteristic impedance corresponding to each of the plurality of sections (FIG. 9, FIG. 15, FIG. 32, equations (15)-(17), paragraphs §0105 -§0114 ; describing microstrip lines with distinct characteristic impedances Z0, Z1, ZE0 to ZE5 for each section to optimize bandwidth).
Regarding claim 7, Hampel further teaches that an admittance value of the shunt admittance is realized using at least one inductor in the circuit, at least one capacitor in the circuit, a series combination of the at least one inductor and the at least one capacitor or a shunt combination of the at least one inductor and the at least one capacitor (FIG. 15, FIG. 25, FIG. 26, equations (19)-(22), paragraphs §0016 , §0152 -§0156 ; showing discrete/distributed reactive elements C0, C1, C2, C3, L forming series/shunt admittance combinations to absorb drain parasites).
Regarding claim 8, Hampel further teaches that the admittance value of the shunt admittance is realized using a transmission line stub with a predefined characteristic impedance value (FIG. 15, FIG. 32, paragraph §0016; low-pass structure implemented by microstrip line impedance steps and stubs acting as reactive shunt admittances).
Conclusion
The prior arts JOSHI (US 2023/0253925 A1) and Kim et al. (US 2008/0191801 A1) are made of record and not relied upon is considered pertinent to applicant's disclosure. Both Joshi and Kim teach a wideband DPA circuit with multi-phasing block component and output impedance transformer and implicit about Parasitic compensators for Main and auxiliary PA.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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