Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments, see page 7, filed 8/22/25, with respect to claims 1-8 and 10-19 have been fully considered and are persuasive. The rejection of claims has been withdrawn.
Applicant argues Parthasarathy fails to teach "storing an index associated with a line in the data cache in a next read index storage element based on the identification; and reading the data from the data cache based on the index". After further consideration. this argument is persuasive. Although this step is common step for the allocation of a new entry in the directory, Parthasarathy does not specifically show this step.
The claims are rejected under new prior art (see rejection).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 10-14, and 18 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parthasarathy et al (US20040073749, “Parthasarathy” in view of Salisbury et al (US20160350220), “Salisbury”).
As to claim 1, 12:
Parthasarathy teaches a method for memory access (method; Claims 15-21), associated apparatus unit comprising a memory (Fig. 1; apparatus having cache and main/system memory; 0002, 0014) and read controller (cache controller; 0018, 0022) perform the operations/process comprising:
identifying whether data to be accessed is stored in a data cache coupled to a memory (0023: “A determination is made regarding whether the instruction fetch request involves a cache access (step 202)”; 0019: “processors typically perform cache accesses in a single cycle. The cache index is utilized to access an entire cache line 106a-106n within both the cache directory 103 and the cache memory 104, tag comparisons are performed within the cache directory 103 to identify the appropriate way 107a-107n, then a late select based on the tag comparisons is employed to output the correct way from the cache memory 104.”).
Parthasarathy teaches the use of the cache directory for cache lookup but does not specifically teach storing an index associated with a line in the data cache in a next read index storage element based on the identification. It is well-known in the art to allocate and add/store a new entry in the cache directory when the requested data is not currently cached by any of the cache memories. Salisbury teaches the first step carried out in a memory access is to check the cache directory to see if it is currently cached; 0146). If it is not currently cached, an allocation of a new entry (snoop vector) is done and this entry is written to the cache directory; 0150-0154; steps 1205-1250; Fig. 12). Salisbury teaches the stored snoop directory entry comprises a tag and snoop vector, is used to index and access the cache line (0091-0096). It would have been obvious to one of ordinary skills in the art, to use Salisbury’s teaching of adding an entry to the cache directory when it is determined that the data is not currently cached in the cache memory so that the cache system of Parthasarathy can further add and store new data to the cache, improving data lookup speed.
Parthasarathy teaches reading, by a processing unit, the data from the data cache based on the stored index stored in the cache directory (0019; “The cache index is utilized to access an entire cache line 106a-106n within both the cache directory 103 and the cache memory 104”). Salisbury also teaches using the stored cache directory entry (comprises a tag and snoop vector) to index and access the cache line (0091-0096).
As to claim 2, 13:
Salisbury further teaches identifying whether the data is stored in the data cache comprises identifying that the data is not stored in the data cache; allocating the line in the data cache based on the data not being stored in the data cache; and transferring the data from the memory to the line in the data cache based on the identification (the first step carried out in a memory access is to check the cache directory to see if it is currently cached; 0146; if it is not currently cached, an allocation of a new entry (snoop vector) is done and this entry is written to the cache directory; 0150-0154; steps 1205-1250; Fig. 12).
As to claim 3, 14:
Parthasarathy teaches identifying whether the data is stored in the data cache comprises identifying that the data was previously stored in the data cache at the line in the data cache associated with the index (access cache tags and generate hit signal for way select, which is used to select the way withing the cache memory during the next cycle to read the data; 0022).
As to claim 7, 18:
Parthasarathy teaches identifying whether the data to be accessed is stored in the data cache comprises identifying whether an address associated with the data in the memory is in a tag array storage element (cache access based on tag comparisons; 0018-0020).
As to claim 10:
Parthasarathy teaches the memory comprises a tightly-coupled memory (TCM) (cache and system memory are always close/tight with the processor; 0014). Salisbury also teaches cache memory 210 is closely coupled to CPU 200; 0069; Fig. 2).
As to claim 11:
Parthasarathy teaches the index is stored in the next read index storage element multiple cycles prior to the data being read from the data cache and processed (cache directory stores previously accessed cache entries; 0018-0021; pipelined cache access may alternatively be performed with a latency of two cycles, initially accessing the indexed cache line only within the cache directory 103 and performing tag comparisons to determine the correct way, then accessing only the hit way within the proper cache line for the cache memory; 0018-0021, 0023-0025). Salisbury also teaches the directory storing entries of previous cache accesses (0146-0148).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6, 8, 9, 15-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Parthasarathy et al (US20040073749, “Parthasarathy), in view of Salisbury et al (US20160350220), “Salisbury” and Yudanov et al (US20240070107, “Yudanov”).
As to claim 4, 5, 15, 16:
Parthasarathy in view of Salisbury does not further teach the next read index storage element comprises a first in first out (FIFO) storage element and transferring data from the data cache to the FIFO for further processing. Storing data in a FIFO storage for fast retrieval is well known in the art for its simplicity and guarantee of the data order. Yudanov teaches a CPU subsystem that includes two pipeline stages using a prefetch-buffer, a FIFO to store instructions from memory, maintaining a proper order of data (0036-0043). Yudanov is an analogous art, also in the field of memory access and control. One of ordinary skills in the art, at the time of the invention, to adapt the cache system of Parthasarathy and Salisbury to use a FIFO storage element for storage data from the cache for further processing, as suggested by Yudanov, to maintain a proper order of data.
As to claim 6, 17:
Parthasarathy teaches performing the operation comprises performing a multiplication operation (processor is multiply-accumulate (MAC) unit; 0015).
As to claim 8, 9, 19:
Parthasarathy in view of Salisbury teaches a caching system with improved performance (0002). Parthasarathy in view of Salisbury does not teach the caching of data comprises weight data for a neural network and multiplying it with activation data. Yudanov teaches storing data for a neural network (abstract, 0020-0021) and (0016, 0169, 0185) and perform computation of data using a multiply-accumulate (MAC) engine (0009), 0021, 0037, 0049). It would have been obvious to one of ordinary skills in the art, at the time of the invention, to implement the caching system of Parthasarathy and Salisbury, in the neural network environment of Yudanov, to store and multiply weight and activation data, to provide for a higher perform caching system in the neural network system of Yudanov.
Allowable Subject Matter
Claim 20 is allowed.
As to claim 20, the prior art does not suggest a neural processing unit, comprising: a memory; a memory read controller configured to identify whether weight data to be accessed is stored in a weight data cache coupled to the memory; a next read index first-in-first-out (FIFO) storage element configured to store an index associated with a line in the weight data cache in a next read index storage element based on the identification; and a multiplier circuit configured to multiply activation data and the weight data from the weight data cache based on the index.
Conclusion
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/THAN NGUYEN/Primary Examiner, Art Unit 2138