DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 9, 10, 13, 14, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Paini (US 2024/0346358).
Regarding claims 1, 10, and 17, fig. 4 of Paini discloses a system, comprising: a memory [402] that stores computer executable components; and a processor (of 404), operably coupled to the memory, that executes the computer executable components stored in the memory, wherein the computer executable components comprise: an input component that receives a setpoint having a phase [that to 466b] or a frequency for a quantum signal (e.g. Abstract, par. 158) as input from registers (from the memory and processor of fig. 4); and an execution component that generates a kernel [472, 462b] based on the setpoint for the quantum signal using a logic block in an integrated circuit, wherein the logic block comprises a numerically controlled oscillator (NCO) [464b] that generates the kernel using a reading of a waveform lookup table [in scheduler 452 for controlling 470] (par. 157).
Regarding claims 5, 13, and 20, fig. 4C and 4D of Paini discloses wherein the execution component generates more than one kernel using a plurality of logic blocks in the integrated circuit, and wherein the waveform lookup table is shared between the plurality of logic blocks (fig. 4 shows where memory and processor controls plurality of FPGA firmware).
Regarding claims 6 and 14, fig. 4C and 4D of Paini discloses wherein the more than one logic blocks are configured to determine different qubit measurements.
Regarding claim 7, fig. 4C and 4D of Paini discloses wherein the waveform lookup table comprises a fixed memory size in the integrated circuit (as indicated by memory).
Regarding claim 9, fig. 4C and 4D of Paini discloses wherein the logic block in the integrated circuit is implemented using a Field-Programmable Gate Array (FPGA) [470] or an Application-Specific Integrated Circuit (ASIC).
Allowable Subject Matter
Claims 2-4, 8, 11, 12, 15, 16, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Nagy describes a method for accelerating operations and accelerator apparatus. Wu describes a loop gain calibration apparatus for controlling loop gain timing. Whitehead describes an unbiased code phase discriminator.
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/SIBIN CHEN/Primary Examiner, Art Unit 2836
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