DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in India on 10/03/23. It is noted, however, that applicant has not filed a certified copy of the IN202341066168 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/08/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tran et al., US 11,722,130
Regarding claim 1, Tran discloses a circuit comprising: a transistor device arranged between a first terminal and a second terminal (Fig. 3; MOSFET 110); a transistor device controller configured to control operation of the transistor device (Fig. 3; gate driver 160); and a current limit controller comprising a current limit circuit configured to regulate an amplitude of operational current through the transistor device between the first and second terminals during a normal operating mode (Fig. 3; current limiter 170 connected to MOSFET 110), and further comprising a testing system configured to conduct a calibration current provided by an automated testing equipment (ATE) device through an internal test resistor for the ATE device (Fig. 3-4a; current sense circuit 130 having a resistor 132 and amp 134 connected to controller 200 considered an automated testing equipment since the metes and bounds of automated testing equipment are not defined by the claim) to determine a resistance value of the internal test resistor during a test mode (Fig. 4a; Sense resistor 132 value monitored to determine current) to facilitate testing of the current limit circuit via a test current provided by the ATE device between the first and second terminals through the transistor device based on the determined resistance value of the internal test resistor (Fig. 4a; resistance value from 132 to amplifier 134 which is a signal corresponding to the load current and is used to control a gate driver to activate or deactivate the MOSFET 110 ).
Regarding claim 2, Tran teaches wherein the current limit controller is coupled to a third terminal that is adapted to receive an external resistor to set a threshold for the amplitude of the operational current at which the current limit circuit is activated during the normal operating mode (Col. 10 lines 5-30; load device considered an external resistor as it comprises a resistance; load current being greater than a threshold results in a resistive short circuit condition and protection circuit 100 shuts off high current to load), wherein the testing system is configured to conduct the calibration current from the ATE device through the internal test resistor via the third terminal (feedback loop from current sensor 130 to controller 200).
Regarding claim 3, Tran teaches wherein the testing system is configured to facilitate the testing of the current limit circuit by conducting a limit current that is proportional to the test current through the internal test resistor after determining the resistance value of the internal test resistor (Fig. 4a; feedback from the sense resistor 132 to amp 134 and controller 200).
Regarding claim 11, Tran discloses a method for testing a current limit circuit of a device-under-test (DUT) circuit, the method comprising: coupling an automated testing equipment (ATE) device to a first terminal, a second terminal, and a third terminal of the DUT circuit (Fig. 3-4a; MOSFET 110 having three terminals with current sensor 130 considered the DUT circuit; all other elements of circuit considered to be the automated testing equipment); setting the DUT circuit to a test mode (Fig. 3, 7; activation of the switch device considered to be a test mode); providing a calibration voltage to the third terminal to conduct a calibration current through an internal test resistor of the DUT circuit that is coupled to the third terminal to determine a resistance value of the internal test resistor (Fig. 3-4a; current conducted through sense resistor 132 based on voltage provided to gate of MOSFET 110); and providing a testing voltage across the first and second terminals to conduct a test current through a transistor device of the DUT circuit (Fig. 3; MOSFET 110) controlled by the current limit circuit based on the resistance value of the internal test resistor (Fig. 3; current limiter 170 connected to MOSFET 110).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al., US 11,722,130 in view of Suzuki, US 20090184748
Regarding claim 12, Tran is silent in wherein the current limit circuit comprises: a current limiter arranged between the first and second terminals of the circuit and being configured to provide a limit current that is proportional to the test current; a control loop transistor device coupled between the current limiter and a control loop terminal and configured to conduct the limit current; and a control loop amplifier configured to control the control loop transistor device based on a voltage of the control loop terminal and a reference voltage. Suzuki teaches a current limiter arranged between the first and second terminals of a circuit and being configured to provide a limit current that is proportional to a test current (Fig. 3; current limiting circuit 20 arranged between gate and source/drain of transistor T24); a control loop transistor device coupled between the current limiter and a control loop terminal and configured to conduct the limit current (Fig. 3; transistor T23 arrange between gate of T24 and having gate coupled to current limit circuit 20); and a control loop amplifier configured to control the control loop transistor device based on a voltage of the control loop terminal and a reference voltage (Fig. 3; amplifier 25 connected to gate of T23 and having a reference voltage). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Suzuki into Tran for the benefit of controlling an excessive current in the transistor device.
Allowable Subject Matter
Claim 16-20 are allowed.
Claims 4-10, 13-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, prior art does not disclose or suggest: “the current limit controller comprising a testing system configured to conduct a calibration current through an internal test resistor during a first phase of a test mode and to conduct a limit current that is proportional to a test current through the internal test resistor during a second phase of the test mode…the ATE device being configured to provide the calibration current via the first terminal through the internal test resistor during the first phase of the test mode to determine a resistance value of the internal test resistor, and to provide the test current through the transistor device between the first and second terminals to test functional operation of the current limit circuit based on the determined resistance value of the internal test resistor” in combination with all the limitations of claim 16.
Regarding claim 4, Prior art does not disclose or suggest: “the testing system comprises a switch controller configured to provide a plurality of switching signals to control a respective plurality of switches during the test mode to facilitate conduction of the calibration current through the internal test resistor and to facilitate conduction of the limit current through the internal test resistor during the test mode” in combination with all the limitations of claim 4.
Regarding claim 8, prior art does not disclose or suggest: “ wherein the test mode comprises: a first phase during which the testing system conducts the calibration current provided by the ATE device through the internal test resistor for the ATE device to determine the resistance value of the internal test resistor; and a second phase subsequent to the first phase during which the ATE device provides predefined voltages to each of the first and second terminals to provide the test current through the transistor device to test the current limit circuit based on the determined resistance value of the internal test resistor” in combination with all the limitations of claim 8.
Regarding claim 13, prior art does not disclose or suggest: “wherein setting the DUT circuit to the test mode comprises: controlling a plurality of switches in a first phase of the test mode to deactivate the control loop transistor device and to conduct the calibration current through the internal test resistor to determine the resistance value of the internal test resistor; and controlling the switches in a second phase of the test mode to activate the control loop transistor device and to conduct the limit current through the control loop transistor device and through the internal test resistor to test the current limit circuit” in combination with all the limitations of claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tadepalli et al., US 20210080498 discloses a system for testing a transistor device including a current limiting circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEBA POTHEN whose telephone number is (571)272-9219. The examiner can normally be reached 8:30-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on 571.272.2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FEBA POTHEN/Examiner, Art Unit 2858