DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 and 12-21 of copending Application No. 18/545361(reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because following observation is made:
Instant Application
Application No. 18/545361
1. A core cluster, comprising: a phase-locked loop (PLL); and a plurality of processor cores based on a common instruction set architecture (ISA), wherein: each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; the plurality of processor cores comprises a first subset of processor cores and a second subset of processor cores; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores than that of each processor core of the second subset of processor cores.
2. The core cluster of claim 1, further comprising a dynamic voltage and frequency scaling (DVFS) circuit configured to: determine that only one or more processor cores of the first subset of processor cores are active among the plurality of processor cores; and responsive to determining that only the one or more processor cores of the first subset of processor cores are active among the plurality of processor cores, switch the core cluster from a first DVFS state to a second DVFS state higher than the first DVFS state.
3. The core cluster of claim 2, wherein the DVFS circuit is further configured to: determine that one or more processor cores of the second subset of processor cores have become active; and responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switch the core cluster to a third DVFS state lower than the second DVFS state.
4. The core cluster of claim 1, wherein each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented to provide a first clock path between the processor core and the PLL that is faster than a second clock path between each processor core of the second subset of processor cores and the PLL.
5. The core cluster of claim 4, wherein the PLL is physically located closer to the first subset of processor cores than the second subset of processor cores.
6. The core cluster of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being optimized to operate at a first minimum voltage/frequency operating point and a first maximum voltage/frequency operating point; and the first minimum voltage/frequency operating point and the first maximum voltage/frequency operating point are higher than a second minimum voltage/frequency operating point and a second maximum voltage/frequency operating point, respectively, of the second subset of processor cores.
7. The core cluster of claim 6, wherein: the first maximum voltage/frequency operating point corresponds to a peak single-thread frequency; and the second maximum voltage/frequency operating point corresponds to a peak multi-thread frequency that is lower than the peak single-thread frequency.
8. The core cluster of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a first plurality of library cells optimized for the higher operating frequency; and each processor core of the second subset of processor cores is implemented using a second plurality of library cells optimized for energy efficiency.
9. The core cluster of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a plurality of block head switches (BHS); and each processor core of the second subset of processor cores is implemented using a plurality of globally distributed head switches (GDHS).
10. The core cluster of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
1. A processor-based device, comprising: a core cluster comprising: a phase-locked loop (PLL); and a plurality of processor cores based on a common instruction set architecture (ISA), wherein: each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; the plurality of processor cores comprises a first subset of processor cores and a second subset of processor cores; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores than that of each processor core of the second subset of processor cores.
2. The processor-based device of claim 1, wherein the core cluster further comprises a dynamic voltage and frequency scaling (DVFS) circuit configured to: determine that only one or more processor cores of the first subset are active among the plurality of processor cores; and responsive to determining that only the one or more processor cores of the first subset are active among the plurality of processor cores, switch the core cluster from a first DVFS state to a second DVFS state higher than the first DVFS state.
3. The processor-based device of claim 2, wherein the DVFS circuit is further configured to: determine that one or more processor cores of the second subset of processor cores has become active; and responsive to determining that the one or more processor cores of the second subset of processor cores has become active, switch the core cluster to a third DVFS state lower than the second DVFS state.
4. The processor-based device of claim 1, wherein each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented to provide a first clock path between the processor core and the PLL that is faster than a second clock path between each processor core of the second subset of processor cores and the PLL.
5. The processor-based device of claim 4, wherein the PLL is physically located closer to the first subset of processor cores than the second subset of processor cores.
6. The processor-based device of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being optimized to operate at a first minimum voltage/frequency operating point and a first maximum voltage/frequency operating point; and the first minimum voltage/frequency operating point and the first maximum voltage/frequency operating point are higher than a second minimum voltage/frequency operating point and a second maximum voltage/frequency operating point, respectively, of the second subset.
7. The processor-based device of claim 6, wherein: the first maximum voltage/frequency operating point corresponds to a peak single-thread frequency; and the second maximum voltage/frequency operating point corresponds to a peak multi-thread frequency that is lower than the peak single-thread frequency.
8. The processor-based device of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a first plurality of library cells optimized for higher frequency; and each processor core of the second subset of processor cores is implemented using a second plurality of library cells optimized for energy efficiency.
9. The processor-based device of claim 1, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a plurality of block head switches (BHS); and each processor core of the second subset of processor cores is implemented using a plurality of globally distributed head switches (GDHS).
10. The processor-based device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
11. A method for implementing asymmetric processor cores in processor-based devices, comprising: determining, by a dynamic voltage and frequency scaling (DVFS) circuit of a core cluster while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of the core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, wherein: the core cluster comprises a phase-locked loop (PLL); the plurality of processor cores are based on a common instruction set architecture (ISA); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; and responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switching, by the DVFS circuit, the core cluster from a first DVFS state to a second DVFS state lower than the first DVFS state.
12. The method of claim 11, further comprising: determining, by the DVFS circuit, that only the one or more processor cores of the first subset of processor cores are now active among the plurality of processor cores; and responsive to determining that only the one or more processor cores of the first subset of processor cores are now active, switching, by the DVFS circuit, the core cluster to a third DVFS state higher than the second DVFS state.
13. The method of claim 11, wherein each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented to provide a first clock path between the processor core and the PLL that is faster than a second clock path between each processor core of the second subset of processor cores and the PLL.
14. The method of claim 13, wherein the PLL is physically located closer to the first subset of processor cores than the second subset of processor cores.
15. The method of claim 11, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being optimized to operate at a first minimum voltage/frequency operating point and a first maximum voltage/frequency operating point; and the first minimum voltage/frequency operating point and the first maximum voltage/frequency operating point are higher than a second minimum voltage/frequency operating point and a second maximum voltage/frequency operating point, respectively, of the second subset of processor cores.
16. The method of claim 15, wherein: the first maximum voltage/frequency operating point corresponds to a peak single-thread frequency; and the second maximum voltage/frequency operating point corresponds to a peak multi-thread frequency that is lower than the peak single-thread frequency.
17. The method of claim 11, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a first plurality of library cells optimized for the higher operating frequency; and each processor core of the second subset of processor cores is implemented using a second plurality of library cells optimized for energy efficiency.
18. The method of claim 11, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a plurality of block head switches (BHS); and each processor core of the second subset of processor cores is implemented using a plurality of globally distributed head switches (GDHS).
12. A method for implementing asymmetric processor cores in processor-based devices, comprising: determining, by a processor-based device, that only one or more processor cores of a first subset of processor cores of a plurality of processor cores of a core cluster of the processor-based device are active among the plurality of processor cores, wherein: the core cluster comprises a phase-locked loop (PLL); the plurality of processor cores are based on a common instruction set architecture (ISA); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; the plurality of processor cores comprises the first subset of processor cores and a second subset of processor cores; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; and responsive to determining that only the one or more processor cores of the first subset are active among the plurality of processor cores, switching, by a dynamic voltage and frequency scaling (DVFS) circuit of the core cluster, the core cluster from a first DVFS state to a second DVFS state higher than the first DVFS state.
13. The method of claim 12, further comprising: determining, by the DVFS circuit, that one or more processor cores of the second subset of processor cores has become active; and responsive to determining that the one or more processor cores of the second subset of processor cores has become active, switching, by the DVFS circuit, the core cluster to a third DVFS state lower than the second DVFS state.
14. The method of claim 12, wherein each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented to provide a first clock path between the processor core and the PLL that is faster than a second clock path between each processor core of the second subset of processor cores and the PLL.
15. The method of claim 14, wherein the PLL is physically located closer to the first subset of processor cores than the second subset of processor cores.
16. The method of claim 12, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being optimized to operate at a first minimum voltage/frequency operating point and a first maximum voltage/frequency operating point; and the first minimum voltage/frequency operating point and the first maximum voltage/frequency operating point are higher than a second minimum voltage/frequency operating point and a second maximum voltage/frequency operating point, respectively, of the second subset.
17. The method of claim 16, wherein: the first maximum voltage/frequency operating point corresponds to a peak single-thread frequency; and the second maximum voltage/frequency operating point corresponds to a peak multi-thread frequency that is lower than the peak single-thread frequency.
18. The method of claim 12, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a first plurality of library cells optimized for higher frequency; and each processor core of the second subset of processor cores is implemented using a second plurality of library cells optimized for energy efficiency.
19. The method of claim 12, wherein: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a plurality of block head switches (BHS); and each processor core of the second subset of processor cores is implemented using a plurality of globally distributed head switches (GDHS).
19. A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device of a processor-based device to: determine, while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of a core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, wherein: the core cluster comprises a phase-locked loop (PLL); the plurality of processor cores are based on a common instruction set architecture (ISA); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; and responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switch the core cluster from a first dynamic voltage and frequency scaling (DVFS) state to a second DVFS state lower than the first DVFS state.
20. The non-transitory computer-readable medium of claim 19, wherein the computer-executable instructions further cause the processor-based device to: determine that only the one or more processor cores of the first subset of processor cores are now active among the plurality of processor cores; and responsive to determining that only the one or more processor cores of the first subset of processor cores are now active, switch the core cluster to a third DVFS state higher than the second DVFS state.
20. A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device of a processor-based device to: determine that only one or more processor cores of a first subset of processor cores of a plurality of processor cores of a core cluster of the processor-based device are active among the plurality of processor cores, wherein: the core cluster comprises a phase-locked loop (PLL); the plurality of processor cores are based on a common instruction set architecture (ISA); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL; the plurality of processor cores comprises the first subset of processor cores and a second subset of processor cores; each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; and responsive to determining that only the one or more processor cores of the first subset are active among the plurality of processor cores, switch the core cluster from a first dynamic voltage and frequency scaling (DVFS) state to a second DVFS state higher than the first DVFS state.
21. The non-transitory computer-readable medium of claim 20, wherein the computer-executable instructions further cause the processor-based device to: determine that one or more processor cores of the second subset of processor cores has become active; and responsive to determining that the one or more processor cores of the second subset of processor cores has become active, switch the core cluster to a third DVFS state lower than the second DVFS state.
As demonstrated, the claims 1-10 and 12-21 of copending Application No. 18/545361 disclose all the features of claims of the instant application. Thus, it would have been obvious to one of ordinary skill in the art having the claims 1-10 and 12-21 of copending application No. 18/545361 to modify the claims to achieve the features of claims 1-20 of the instant application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 6-11,15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (Hsu) (Pub NO. Us 2016/0062447) (Hsu) in view of Allen et al. (Allen)(Patent No. US 6,963,990)
Regrading Claim 1 Hsu teaches: a core cluster [Fig.1, item 110 and 120] comprising: and a plurality of processor cores based on a common instruction set architecture (ISA), [[0016] same instructions can be executed either by the first cores 110 or by the second cores 120 ] wherein: the plurality of processor cores comprises a first subset of processor cores and a second subset of processor cores; [[0016], Fig.1, item 110, 120] each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; [Fig.1, [0017]-[0018] the performance of each first core 110 is greater than that of each second core 120 ] and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores than that of each processor core of the second subset of processor cores. [[0016]-[0019] slower, low-power processor cores with more powerful and power-hungry ones…. he operating frequency of the active first core 110 may be different from the operating frequency of the active second core 120, and the operating voltage of the active first core 110 may be different from the operating voltage of the active second core 120]
Hsu does not teach a phase-locked loop (PLL); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL.
However, Allen teaches a phase-locked loop (PLL); [Fig.2, item 250] each processor core [Logics 260a-260d corresponds to cores]of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL. [col.5, lines 30-35, four bus logics 260a, 260b, 260c, and 260d operate synchronously from a clock signal generated by PLL circuit 250]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the clock synchronization of Allen’s to synchronize processing cores in Hus’s system to improves performance and enhances reliability of Hus’s system.
Regrading Claim 2 Hsu teaches: the core cluster further comprises a dynamic voltage and frequency scaling (DVFS) circuit configured to: determine that only one or more processor cores of the first subset are active among the plurality of processor cores; and responsive to determining that only the one or more processor cores of the first subset are active among the plurality of processor cores, switch the core cluster from a first DVFS state to a second DVFS state higher than the first DVFS state. [Par.[0020]-[0025], Fig.3, item 301: two entries wherein reference performance and power indexes. The greater the value of the power index B, the greater power is consumed by the multi-core processor 100. Therefore, one of the entries 204 may be selected from the DVFS table 200 according to a power budget and/or a required performance of the multi-core processor 100 by referencing the values of the fields of the performance index A and the power index B.]
Regrading Claim 6 Hsu teaches: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being optimized to operate at a first minimum voltage/frequency operating point and a first maximum voltage/frequency operating point; and the first minimum voltage/frequency operating point and the first maximum voltage/frequency operating point are higher than a second minimum voltage/frequency operating point and a second maximum voltage/frequency operating point, respectively, of the second subset of processor cores. [[0016]-[0019], Fig.1, 110 and 120. Multicore processor whose cores operate at different clock speed]
Regrading Claim 7 Hsu teaches: the first maximum voltage/frequency operating point corresponds to a peak single-thread frequency; and the second maximum voltage/frequency operating point corresponds to a peak multi-thread frequency that is lower than the peak single-thread frequency. [ Table 2, [0024] TLP is calculated according a number of running tasks in run queues of an operating system (OS) of the information system 10, [0025] –[0026] the operating frequency of the P active first core (s) 110 is set to be the first operating frequency F1 of the selected entry 204, and the operating voltage of the P active first core (s) 110 is set to be the first operating voltage V1 of the selected entry 204. Similarly, when the second cores 120 are configured according to the second settings 220 of the selected entry 204, Q second core (s) 120 is active, the operating frequency of the Q active second core (s) 120 is set to be the second operating frequency F2 of the selected entry 204, and the operating voltage of the Q active second core (s) 120 is set to be the second operating voltage V2 of the selected entry 204]
Regrading Claim 8 Hsu teaches: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a first plurality of library cells optimized for higher frequency; and each processor core of the second subset of processor cores is implemented using a second plurality of library cells optimized for energy efficiency. . [[0016]-[0019], Fig.1, 110 and 120. Multicore processor whose cores operate at different clock speed]
Regrading Claim 9 Hsu teaches: each processor core of the first subset of processor cores is implemented with the different physical characteristic by being implemented using a plurality of block head switches (BHS); and each processor core of the second subset of processor cores is implemented using a plurality of globally distributed head switches (GDHS). [[0016]-[0019], Fig.1, 110 and 120. Multicore processor whose cores operate at different clock speed]
Regrading Claim 10 Hsu teaches: integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. [0003]
Regrading Claim 11 Hsu teaches a method for implementing asymmetric processor cores [[0017] performance of each first core 110 is greater than that of each second core 120, Fig.1, item 110 and 120] in processor-based devices, comprising: determining, by a dynamic voltage and frequency scaling (DVFS) circuit [Fig.2, item 200 DVFS table] of a core cluster [Fig.1, item 110 and 120] while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of the core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, [[0021]-[0026] hen the first cores are configured according to the first settings 210 of the selected entry , P first core (s) is active, the operating frequency of the P active first core (s) is set to be the first operating frequency F1 of the selected entry , and the operating voltage of the P active first core (s) is set to be the first operating voltage V1 of the selected entry . Similarly, when the second cores are configured according to the second settings of the selected entry , Q second core (s) is active, the operating frequency of the Q active second core (s) is set to be the second operating frequency F2 of the selected entry , and the operating voltage of the Q active second core (s) is set to be the second operating voltage V2 of the selected entry.] wherein: the plurality of processor cores are based on a common instruction set architecture (ISA); [[0016] same instructions can be executed either by the first cores 110 or by the second cores 120 ]
each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; [Fig.1, [0017]-[0018] the performance of each first core 110 is greater than that of each second core 120 ] and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; [[0016]-[0019] slower, low-power processor cores with more powerful and power-hungry ones…. he operating frequency of the active first core 110 may be different from the operating frequency of the active second core 120, and the operating voltage of the active first core 110 may be different from the operating voltage of the active second core 120]
and responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switching, by the DVES circuit, the core cluster from a first DVFS state to a second DVEFS state lower than the first DVES state, [Par.[0020]-[0025], Fig.3, item 301: two entries wherein reference performance and power indexes. The greater the value of the power index B, the greater power is consumed by the multi-core processor 100. Therefore, one of the entries 204 may be selected from the DVFS table 200 according to a power budget and/or a required performance of the multi-core processor 100 by referencing the values of the fields of the performance index A and the power index B.]
Hsu does not teach the core cluster comprises a phase-locked loop (PLL); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL;
However, Allen teaches a phase-locked loop (PLL); [Fig.2, item 250] each processor core [Logics 260a-260d corresponds to cores]of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL. [col.5, lines 30-35, four bus logics 260a, 260b, 260c, and 260d operate synchronously from a clock signal generated by PLL circuit 250]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the clock synchronization of Allen’s to synchronize processing cores in Hus’s system to improves performance and enhances reliability of Hus’s system.
Claim 15 is having similar limitations to that of the apparatus of claim 6. Accordingly, claim15 is rejected under a similar rational as that of claim 6 above.
Claim 16 is having similar limitations to that of the apparatus of claim 7. Accordingly, claim16 is rejected under a similar rational as that of claim 7 above.
Claim 17 is having similar limitations to that of the apparatus of claim 8. Accordingly, claim17 is rejected under a similar rational as that of claim 8 above.
Claim 18 is having similar limitations to that of the apparatus of claim 9. Accordingly, claim18 is rejected under a similar rational as that of claim 9 above.
19. A non-transitory computer-readable medium, having stored thereon computer- executable instructions that, when executed, cause a processor device of a processor- based device to: [[0006] [0020] computing system reads instructions from a computer-readable medium to execute a power management process to dynamically adjust power settings of the first cores and the second cores]
determine, while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of a core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, [[0021]-[0026] hen the first cores are configured according to the first settings 210 of the selected entry , P first core (s) is active, the operating frequency of the P active first core (s) is set to be the first operating frequency F1 of the selected entry , and the operating voltage of the P active first core (s) is set to be the first operating voltage V1 of the selected entry . Similarly, when the second cores are configured according to the second settings of the selected entry , Q second core (s) is active, the operating frequency of the Q active second core (s) is set to be the second operating frequency F2 of the selected entry , and the operating voltage of the Q active second core (s) is set to be the second operating voltage V2 of the selected entry.] wherein: the plurality of processor cores are based on a common instruction set architecture (ISA); [[0016] same instructions can be executed either by the first cores 110 or by the second cores 120 ]
each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores; [Fig.1, [0017]-[0018] the performance of each first core 110 is greater than that of each second core 120 ] and the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores; ; [[0016]-[0019] slower, low-power processor cores with more powerful and power-hungry ones…. he operating frequency of the active first core 110 may be different from the operating frequency of the active second core 120, and the operating voltage of the active first core 110 may be different from the operating voltage of the active second core 120]
and responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switch the core cluster from a first dynamic voltage and frequency scaling (DVES) state to a second DVFES state lower than the first DVES state [Par.[0020]-[0025], Fig.3, item 301: two entries wherein reference performance and power indexes. The greater the value of the power index B, the greater power is consumed by the multi-core processor 100. Therefore, one of the entries 204 may be selected from the DVFS table 200 according to a power budget and/or a required performance of the multi-core processor 100 by referencing the values of the fields of the performance index A and the power index B.] Hsu does not teach the core cluster comprises a phase-locked loop (PLL); each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL;
However, Allen teaches a phase-locked loop (PLL); [Fig.2, item 250] each processor core [Logics 260a-260d corresponds to cores]of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL. [col.5, lines 30-35, four bus logics 260a, 260b, 260c, and 260d operate synchronously from a clock signal generated by PLL circuit 250]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use the clock synchronization of Allen’s to synchronize processing cores in Hus’s system to improves performance and enhances reliability of Hus’s system.
Claims 3, 12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (Hsu) (Pub NO. Us 2016/0062447) (Hsu) in view of Allen et al. (Allen)(Patent No. US 6,963,990) further in view of Mathieson et al. (Pub NO. US 2011/0213998)
Regarding Claim 3 the combination of Hsu and Allen does not teach that the DVFS circuit is further configured to: determine that one or more processor cores of the second subset of processor cores has become active; and responsive to determining that the one or more processor cores of the second subset of processor cores has become active, switch the core cluster to a third DVFS state lower than the second DVFS state.
However, Mathieson teaches: the DVFS circuit is further configured to: determine that one or more processor cores of the second subset of processor cores has become active; and responsive to determining that the one or more processor cores of the second subset of processor cores has become active, switch the core cluster to a third DVFS state lower than the second DVFS state. [[0043] When execution of the processing operations switches from the first set of cores to the second set of cores, in some embodiments, the controller 240 is configured to transfer the processor state from the first set of cores to the second set of cores. In one embodiment, the controller saves the processor state to the shared resource 230, triggers a hardware mechanism that stops and powers off the first set of cores 210, and boots the second set of cores 220. The second set of cores 220 then restores the processor state from the shared resource 230 and continues operation at the lower speed associated with the second set of cores 220. [0077] a dynamic voltage and frequency scaling (DVFS), may be implemented to vary the voltage and/or operating frequency of the active cores. Again, according to various embodiments, vary the voltage and/or operating frequency of the active cores may cause the processor to operate at a lower total power consumption, thereby reducing the power required to executing the processing operations. ]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention DVFS of Mathieson to adjust voltage and frequency in Hsu’s system to reduce overall power consumption of Hsu’s system.
Claims 12 and 20 are having similar limitations to that of the apparatus of claim 3. Accordingly, claims 12 and 20 are rejected under a similar rational as that of claim 3 above.
Claims 4-5 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (Hsu) (Pub NO. Us 2016/0062447) (Hsu) in view of Allen et al. (Allen)(Patent No. US 6,963,990) further in view of Jain et al. (Pub No. US 2023/0315141)(Jain)
Regarding Claim 4 Hsu teaches each processor core of the first subset of processor cores is implemented with the different physical characteristic [[0016]-[0019] slower, low-power processor cores with more powerful and power-hungry ones…. he operating frequency of the active first core 110 may be different from the operating frequency of the active second core 120, and the operating voltage of the active first core 110 may be different from the operating voltage of the active second core 120]
The combination of Hsu and Allen does no teach to provide a first clock path between the processor core and the PLL that is faster than a second clock path between each processor core of the second subset of processor cores and the PLL.
However, Jain teaches to provide a first clock path [Fig.1 CLK03] between the processor core [Fig. 1 Functional block 142-3] and the PLL [Fig.1 PLL 110]that is faster than a second clock path [Fig.1, CLK02] between each processor core of the second subset of processor cores [Fig.1 Functional Circuit 142-2 ] and the PLL. [Fig.1]
Therefore, it would have been obvious to one of the ordinary skilled in the art to which this invention pertains before the effective filing date of the invention to use PLL circuit configuration of Jain in Hsu’s system to optimize performance and improve power efficiency of the system.
Regrading Claim 5 Jain teaches the PLL is physically located closer to the first subset of processor cores than the second subset of processor cores. [Fig.1, Between the PLL 110 and Functional circuit 142-3 is less than the distance between the PLL and the functional circuit 142-2]
Claim 13 is having similar limitations to that of the apparatus of claim 4. Accordingly, claim13 is rejected under a similar rational as that of claim 4 above.
Claim 14 is having similar limitations to that of the apparatus of claim 5. Accordingly, claim 14 is rejected under a similar rational as that of claim 5 above.
Conclusion
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/ZAHID CHOUDHURY/Primary Examiner, Art Unit 2175