Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/8/2026 has been entered.
Other Refs: Lee (US 20220317931 A1) – scheduling operations in memory devices in a system
Das (US 20240329879) isolation in multi-tenant storage device.
Non-Patent Literature - Cockburn, B.F.; Tutorial on Semiconductor Memory Testing (Journal of Electronic Testing 1994)(attached) – relates to claimed memory device development system.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,4,5,9,12,13,17,18 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash (US 20230409230 A1) and in view of Trimberger (US 8872536) and further in view of Zhou (US 20210397170)
Claim 1. Prakash discloses A system (eg., 0022 – system.. flash memory device) comprising:
a memory device development system to execute a development process to produce a plurality of memory devices (eg., 0024 - memory 104 illustrated in FIG. 1 includes a plurality of memory units 107A-107N (for example, flash memory units).; 0039 - method 600 is performed during an initial memory die sorting stage during production of the data storage device 102 (e.g., performed by a manufacturing controller that controls the packaging of the memory dies into the data storage device 102); and
a processing device, operatively coupled with the memory device development system, to perform operations comprising: (eg., 0053 - data storage device controller 106 may implement the memory die management module 124 to perform the method 900.)
analyzing one or more property and capability characteristics of the plurality of memory devices produced in the development process (eg., 0039 - method 600 is performed during an initial memory die sorting stage during production of the data storage device 102 );
identifying respective subsets of the plurality of memory devices having property and (eg., 0040 - sorting of the memory dies has just been initiated and no memory dies have been sorted, an initial (e.g., a first) memory die may be selected. The memory dies may be, for example, the memory units 107A-107N within the memory 104.; 0037 - This value varies between memory dies; 0052 - memory die selection process (at block 815)); and
allocating the respective subsets to groups of memory devices corresponding to the different use cases (eg., 0053 - FIG. 9 provides a method 900 for allocating data within the memory dies based on how often the data is read.; 0054 - the data storage device controller 106 compares how often data stored in the memory die is read (e.g., a cumulative read occurrence) to a read threshold ).
Prakash does not disclose, but Trimberger discloses
wherein the development process comprises a plurality of stages, and wherein memory devices produced at each stage have improved property and capability characteristics relative to a previous stage (eg., col 4:65 – col 5:10 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade));
capability characteristics that meet respective standards associated with a plurality of different use cases (eg., col 2:65- col 3:11 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, providing the benefit of desirable to minimize the number of lower performing dies that are packaged when manufacturing and fulfilling orders for high performance dies (see Trimberger, col 2:1-5).
Prakash in view of Trimberger does not disclose, but Zhou discloses
over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system (e.g., 0068 neural network can also be trained to look for other aspects, such as semi-circles or elliptical shapes. Statistics, such as expected Circular Memory holes per image vs. Expected Data, can be generated and fed back for improvements in the fabrication process; 0075 - testing can be done as part of a normal test process during fabrication or in response to the occurrence of failed devices as part of failure analysis. The testing can also be done as part of a sorting or binning process (separating devices into lots of good/bad, good/bad/marginal, and or so) or monitor processing, where the results can be used to go back and adjust processing parameters )
( Additionally, the amended limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, is non-functional descriptive language in computer context (MPEP subsection 2111.05 and/or 2114.II Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)), as supporting information or data rather than a functional relationship between the other limitations of the processing device. This limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system is merely an abstract statement but does not have a functional relationship with the other limitations. For example, if the limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system was removed from the claim, the claim would have exactly the same functional relationships and patentable weight. Thus, the limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, are interpreted under broadest reasonable interpretation in combination with the other limitations; Further, one of ordinary skill would not have known how the claim limitations measure incrementally improved property and capability characteristics);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, with Zhou, providing the benefit of testing can occur at many stages during manufacturing and also afterwards to determine defects and process variations. The testing results can be used to determine defective, or potentially defective, devices, sort devices according to their characteristics, or to adjust processing parameters. To be able to perform these test processes more accurately and efficiently, the following presents a number of techniques using Convolution Neural Networks (CNNs) (see Zhou, 0043).
Claim 4. Prakash discloses wherein the respective standards associated with the plurality of different use cases comprise a respective minimum level of properties and capabilities associated with each of the plurality of different uses cases (eg., 0054 - a read threshold.; 0058 - “hot” data is moved to memory dies in the second VSG memory die group, the space available to store data within the second VSG memory die group decreases. Accordingly, “cold” data that experiences less read events may be moved from memory dies within the second VSG memory die group to memory dies within the first VSG memory die group.)
Claim 5. Prakash discloses wherein the plurality of different uses cases comprise one or more of client systems, mobile applications, enterprise data centers, automotive applications, industry systems, or removable storage devices (eg., 0023 - host device 108 is configured to provide data 110 (for example, user data 136) to the data storage device 102 to be stored, for example, in the memory 104. The host device 108 is, for example, a smart phone, a music player, a video player, a gaming console, an e-book reader, a personal digital assistance device, a tablet, a notebook computer, or another similar device).
Claim 9. Prakash discloses A method (eg., 0022 – system.. flash memory device) comprising:
analyzing one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system (eg., 0039 - method 600 is performed during an initial memory die sorting stage during production of the data storage device 102 );
identifying respective subsets of the plurality of memory devices having property and (eg., 0040 - sorting of the memory dies has just been initiated and no memory dies have been sorted, an initial (e.g., a first) memory die may be selected. The memory dies may be, for example, the memory units 107A-107N within the memory 104.; 0037 - This value varies between memory dies; 0052 - memory die selection process (at block 815)); and
allocating the respective subsets to groups of memory devices corresponding to the different use cases (eg., 0053 - FIG. 9 provides a method 900 for allocating data within the memory dies based on how often the data is read.; 0054 - the data storage device controller 106 compares how often data stored in the memory die is read (e.g., a cumulative read occurrence) to a read threshold ).
Prakash does not disclose, but Trimberger discloses
wherein the development process comprises a plurality of stages, and wherein memory devices produced at each stage have improved property and capability characteristics relative to a previous stage (eg., col 4:65 – col 5:10 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade));
capability characteristics that meet respective standards associated with a plurality of different use cases (eg., col 2:65- col 3:11 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, providing the benefit of desirable to minimize the number of lower performing dies that are packaged when manufacturing and fulfilling orders for high performance dies (see Trimberger, col 2:1-5).
Prakash in view of Trimberger does not disclose, but Zhou discloses
over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system (e.g., 0068 neural network can also be trained to look for other aspects, such as semi-circles or elliptical shapes. Statistics, such as expected Circular Memory holes per image vs. Expected Data, can be generated and fed back for improvements in the fabrication process; 0075 - testing can be done as part of a normal test process during fabrication or in response to the occurrence of failed devices as part of failure analysis. The testing can also be done as part of a sorting or binning process (separating devices into lots of good/bad, good/bad/marginal, and or so) or monitor processing, where the results can be used to go back and adjust processing parameters )
( Additionally, the amended limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, is non-functional descriptive language in computer context (MPEP subsection 2111.05 and/or 2114.II Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)), as supporting information or data rather than a functional relationship between the other limitations of the processing device. This limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system is merely an abstract statement but does not have a functional relationship with the other limitations. For example, if the limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system was removed from the claim, the claim would have exactly the same functional relationships and patentable weight. Thus, the limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, are interpreted under broadest reasonable interpretation in combination with the other limitations; Further, one of ordinary skill would not have known how the claim limitations measure incrementally improved property and capability characteristics);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, with Zhou, providing the benefit of testing can occur at many stages during manufacturing and also afterwards to determine defects and process variations. The testing results can be used to determine defective, or potentially defective, devices, sort devices according to their characteristics, or to adjust processing parameters. To be able to perform these test processes more accurately and efficiently, the following presents a number of techniques using Convolution Neural Networks (CNNs) (see Zhou, 0043).
Claim 12 is rejected for reasons similar to Claim 4 above.
Claim 13 is rejected for reasons similar to Claim 5 above.
Claim 17. Prakash discloses A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (eg., 0022 – system.. flash memory device) comprising:
analyzing one or more property and capability characteristics of a plurality of memory devices produced in a development process executed by a memory device development system (eg., 0039 - method 600 is performed during an initial memory die sorting stage during production of the data storage device 102 );
identifying respective subsets of the plurality of memory devices having property and (eg., 0040 - sorting of the memory dies has just been initiated and no memory dies have been sorted, an initial (e.g., a first) memory die may be selected. The memory dies may be, for example, the memory units 107A-107N within the memory 104.; 0037 - This value varies between memory dies; 0052 - memory die selection process (at block 815)); and
allocating the respective subsets to groups of memory devices corresponding to the different use cases (eg., 0053 - FIG. 9 provides a method 900 for allocating data within the memory dies based on how often the data is read.; 0054 - the data storage device controller 106 compares how often data stored in the memory die is read (e.g., a cumulative read occurrence) to a read threshold ).
Prakash does not disclose, but Trimberger discloses
wherein the development process comprises a plurality of stages, and wherein memory devices produced at each stage have improved property and capability characteristics relative to a previous stage (eg., col 4:65 – col 5:10 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade));
capability characteristics that meet respective standards associated with a plurality of different use cases (eg., col 2:65- col 3:11 - quality metric can be, for example, the following: (a) a performance of the die (e.g., speed); (b) a power consumption of the die; (c) a functionality of the die (e.g., the amount of usuable memory on the die, a number of functional processors on the die, a number of functional processors on the die that satisfy a functional processor constraint, a number of functional through die vias (TDVs), and a number of components satisfying a temperature grade)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, providing the benefit of desirable to minimize the number of lower performing dies that are packaged when manufacturing and fulfilling orders for high performance dies (see Trimberger, col 2:1-5).
Prakash in view of Trimberger does not disclose, but Zhou discloses
over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system (e.g., 0068 neural network can also be trained to look for other aspects, such as semi-circles or elliptical shapes. Statistics, such as expected Circular Memory holes per image vs. Expected Data, can be generated and fed back for improvements in the fabrication process; 0075 - testing can be done as part of a normal test process during fabrication or in response to the occurrence of failed devices as part of failure analysis. The testing can also be done as part of a sorting or binning process (separating devices into lots of good/bad, good/bad/marginal, and or so) or monitor processing, where the results can be used to go back and adjust processing parameters )
( Additionally, the amended limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, is non-functional descriptive language in computer context (MPEP subsection 2111.05 and/or 2114.II Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)), as supporting information or data rather than a functional relationship between the other limitations of the processing device. This limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system is merely an abstract statement but does not have a functional relationship with the other limitations. For example, if the limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system was removed from the claim, the claim would have exactly the same functional relationships and patentable weight. Thus, the limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, are interpreted under broadest reasonable interpretation in combination with the other limitations; Further, one of ordinary skill would not have known how the claim limitations measure incrementally improved property and capability characteristics);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, with Zhou, providing the benefit of testing can occur at many stages during manufacturing and also afterwards to determine defects and process variations. The testing results can be used to determine defective, or potentially defective, devices, sort devices according to their characteristics, or to adjust processing parameters. To be able to perform these test processes more accurately and efficiently, the following presents a number of techniques using Convolution Neural Networks (CNNs) (see Zhou, 0043).
Claim 18 is rejected for reasons similar to Claims 4 and 5 above.
Claims 2, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash (US 20230409230 A1) and in view of Trimberger (US 8872536) and Zhou (cited above) and further in view of Nguyen (US 20220199165 A1)
Claim 2. Prakash in view of Trimberger and Zhou does not disclose, but Nguyen discloses
wherein the one or more property and capability characteristics comprise a read window budget (RWB) of the plurality of memory devices (eg., 0046 - Since each group has fewer than 16 programming distributions, the RWB between those distributions will be greater).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash in view of Trimberger, and Zhou with Nguyen, providing the benefit of thereby allowing the corresponding memory cells to be read with less errors (see Nguyen 0046) A non-volatile memory device is a package of one or more dies (0011).
Claim 10 is rejected for reasons similar to Claim 2 above.
Claims 3, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash (US 20230409230 A1) and in view of Trimberger (US 8872536) and Zhou (cited above) and further in view of Sharon (US 20180262215 A1) and Peh (US 20210026547)
Claim 3. Prakash discloses wherein the one or more property and capability characteristics (eg., 0026 - power manager 140 receives the performance metrics 130 from module 110A and performance metrics 132 from module 110B. These performance metrics 130 and 132 are values stored in performance counters across the dies 122A-122B and dies 122C-122D.)
Prakash in view of Trimberger and Zhou does not disclose, but Sharon discloses
comprise one or more of endurance, data retention capability, read disturb tolerance, latent read disturb tolerance (eg., 0070 - endurance or retention issues (e.g., a memory element has exceeded a certain threshold number of program/erase cycles), or as a result of program disturb), or a number of bitlines/columns available to the user of the plurality of memory devices (eg., [0069] Referring back to FIG. 3, the organizational arrangement or hierarchy may also group the bitlines (BL) into groups (otherwise referred to as columns) of bitlines (BL). Grouping the bitlines may reduce the complexity of addressing the storage locations of the array in that a column address over a page may be identified on the basis of groups (or columns) of bitlines,; 0070 - elements may store data unreliably from the beginning of its life, such as upon being manufactured, or may initially store data reliably, but may then store data unreliably after a period of operation) a number of blocks/pages available to a user,
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash in view of Trimberger and Zhou with Sharon, providing the benefit of estimated reliability characteristic values for the data set (see Sharon, 0020) updated set of reliability metric values (0021).
Prakash in view of Trimberger and Zhou and Sharon does not disclose, but Peh discloses
a number of blocks/pages available to a user (eg., 0027 - memory controller 115 can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host device 105 and the memory device 110, or maintaining integrity of stored data (e.g., using redundant RAID storage, etc.), and can remove (e.g., retire) failing memory resources (e.g., memory cells, memory arrays, pages, blocks, etc.) to prevent future errors.),
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash in view of Trimberger and Zhou with Sharon, with Peh providing the benefit of runtime allocation to avoid memory defects memory sub-systems so that defective or marginal physical erase blocks are not allocated until certain criteria are met (see Peh, 0013).
Claim 11 is rejected for reasons similar to Claim 3 above.
Claims 7, 15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash (US 20230409230 A1) and in view of Trimberger (US 8872536) and Zhou (cited above) and further in view of Benisty (US 20210409038 A1)
Claim 7. Prakash in view of Trimberger and Zhou does not disclose, but Benisty discloses
wherein the processing device is to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize one or more redundant bitlines of the one or more of the plurality of memory devices to store additional parity data. (eg., 0048 - other embodiment, each NAND die includes a fixed number of redundant columns. After production, the dies are screened, and the defective columns are replaced with the redundant columns in order to ensure that each die includes the same amount of acceptable usable capacity).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash in view of Trimberger and Zhou with Benisty, providing the benefit of in order to ensure that each die includes the same amount of acceptable usable capacity .. LBAs may be assigned to certain dies depending on the amount of acceptable usable capacity of the relevant dies (see Benisty, 0048).
Claim 15 is rejected for reasons similar to Claim 7 above.
Claim 19 is rejected for reasons similar to Claim 7 above.
Claims 8, 16, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Prakash (US 20230409230 A1) and in view of Trimberger (US 8872536) and Zhou (cited above) and further in view of Batutis (US 11017870)
Claim 8. Prakash in view of Trimberger and Zhou does not disclose, but Batutis discloses
wherein the processing device is to perform operations further comprising: configuring a memory sub-system controller of a memory sub-system comprising one or more of the plurality of memory devices to utilize an adaptive media scan threshold for the one or more of the plurality of memory devices (eg., col 9:1-10).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash in view of Trimberger and Zhou with Batutis, providing the benefit of periodically performing maintenance operations on the select gate devices to adjust the current threshold voltage of those select gate devices (which can have shifted over time) back to a target threshold voltage. In one embodiment, in response to a request to erase a given data block or a request to invalidate the data block, a memory sub-system controller determines a number of program/erase cycles performed on the data block and determines whether the number of program/erase cycles satisfies a scan threshold condition (see Batutis, col 2:47-56).
Claim 16 is rejected for reasons similar to Claim 8 above.
Claim 20 is rejected for reasons similar to Claim 8 above.
Response to Arguments
Applicant's arguments filed 4/3/2026 (via RCE 5/8/2026) have been fully considered but they are not persuasive.
For claims 1, 9 and 17, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Prakash in view of Trimberger does not disclose, but Zhou discloses
over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system (e.g., 0068 neural network can also be trained to look for other aspects, such as semi-circles or elliptical shapes. Statistics, such as expected Circular Memory holes per image vs. Expected Data, can be generated and fed back for improvements in the fabrication process; 0075 - testing can be done as part of a normal test process during fabrication or in response to the occurrence of failed devices as part of failure analysis. The testing can also be done as part of a sorting or binning process (separating devices into lots of good/bad, good/bad/marginal, and or so) or monitor processing, where the results can be used to go back and adjust processing parameters ); ( Additionally, the amended limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, is non-functional descriptive language in computer context (MPEP subsection 2111.05 and/or 2114.II Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)), as supporting information or data rather than a functional relationship between the other limitations of the processing device. This limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system is merely an abstract statement but does not have a functional relationship with the other limitations. For example, if the limitation of over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system was removed from the claim, the claim would have exactly the same functional relationships and patentable weight. Thus, the limitation over time, and wherein memory devices produced at each successive stage have incrementally improved property and capability characteristics relative to a previous stage due to design changes and process refinements in the memory device development system, are interpreted under broadest reasonable interpretation in combination with the other limitations; Further, one of ordinary skill would not have known how the claim limitations measure incrementally improved property and capability characteristics);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the system with flash memory devices that allocate dies as disclosed by Prakash, with Trimberger, with Zhou, providing the benefit of testing can occur at many stages during manufacturing and also afterwards to determine defects and process variations. The testing results can be used to determine defective, or potentially defective, devices, sort devices according to their characteristics, or to adjust processing parameters. To be able to perform these test processes more accurately and efficiently, the following presents a number of techniques using Convolution Neural Networks (CNNs) (see Zhou, 0043).
Applicant’s arguments for dependent claims 2-5,7-9, 10-13,15-20 are based on their respective base independent claims 1, 9, 17, which are addressed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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