DETAILED ACTION
The current Office Action is in response to the papers submitted 01/22/2026. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Selinger et al. (Pub. No.: US 2011/0161784) referred to as Selinger.
Regarding claim 1, Selinger teaches a memory device [300 and 330, Fig 3; Items 300 and 330 together are a memory device comprised of a controller and a flash memory modules]; and
a host [120, Fig 1] in communication with the memory device [300 and 330, Fig 3] and configured to:
determine a background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; The status information indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3] indicative of whether the memory device [300 and 330, Fig 3] is configured in a first state supporting host controlled enablement [1104 and 1106, Fig 11; The unmanaged state is a first state where the host enables background operations to manage spare blocks] of background operations [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062, 0074 – 0077, and 0091; The status information sent to the host indicates the memory device is enabled to perform certain operations such as a block copy and remapping, returning a block as a spare, manage read/write failures, wear leveling, data relocation, or read scrubbing since the status information causes the host to enable those functions in the memory] or a second state not supporting host controlled enablement of background operations [1108 and 1110, Fig 11; Paragraphs 0062, 0074 – 0077, and 0091; The fully managed spare block mode is a second state where the host is not in control of enabling spare block background operations, the controller is]; and
in response to the memory device being configured in the first state [1104 and 1106, Fig 11], enable or disable the background operations [1106, Fig 11; The management of the spare blocks are background operations and are controlled by the host] of the memory device [300 and 330, Fig 3], wherein the background operations are either enabled to allow the memory device to initiate the background operations independent of the host or disabled to prohibit the memory device [300 and 330, Fig 3] from initiating the background operation [1104 and 1106, Fig 11; Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing. When the host is in control the initiates the background operations not the memory device].
Regarding claim 2, Selinger teaches the host [120, Fig 1] is configured to enable background operations [Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing] of the memory device [300 and 330, Fig 3] via setting one or more bits [3110, Fig 13A; Paragraphs 0104 – 0108; The host sets bits in the commands register based on the command the host sends to the memory device] of the memory device [300 and 330, Fig 3].
Regarding claim 3, Selinger teaches the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077] of the memory device [300 and 330, Fig 3] is determined via one or more bits stored [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] on the memory device [300 and 330, Fig 3].
Regarding claim 4, Selinger teaches the host [120, Fig 1] reads the one or more bits to determine the background operations status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; Sending the status information to the host is equivalent to the host reading the status information to know the status of background operations] of the memory device [300 and 330, Fig 3].
Regarding claim 5, Selinger teaches the host [120, Fig 1] reads [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; Sending the status information to the host is equivalent to the host reading the status information to know the status of background operations] a register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] of the memory device [300 and 330, Fig 3] to determine the background operations status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; The status information indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3].
Regarding claim 6, Selinger teaches the background operations include one or more of wear leveling [Paragraphs 0062 and 0074 – 0077; Wear leveling is listed as an operation], data collection [Paragraphs 0062 and 0074 – 0077; Relocating data from a bad area to a new area is listed which is a form of collecting data from one area to another area], and block erasing [Paragraphs 0062 and 0073 – 0077; The erasing operations can be left to the host to perform].
Regarding claim 7, Selinger teaches the memory device [300 and 330, Fig 3] is configured to initiate a background operation in response to a command from the host [Paragraphs 0062 and 0073 – 0077; The host sends commands related to background operations including wear leveling, data relocation, or read scrubbing].
Regarding claim 8, Selinger teaches memory device [300 and 330, Fig 3] includes one or more of a status register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330], an enablement register, or a time register to store data indicative of the background operation status [3570, Fig 13C; Paragraphs 0062, 0074 – 0077, 0104 and 0120 – 0121; The status register is part of 300 and 330 which stores status information which indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3].
Regarding claim 9, Selinger teaches a memory device [300 and 330, Fig 3], comprising:
a number of memory arrays [330, Fig 3]; and
a controller [300, Fig 3] coupled to the number of memory arrays [330, Fig 3] and including at least one register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] of a number of registers [3110, 3080, 3140, 3150 fig 13A; 3570, Fig 13C] for storing a background operation status [3570, Fig 13C; Paragraphs 0062, 0074 – 0077, 0104 and 0120 – 0121; The status register is part of 300 and 330 which stores status information which indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3] indicative of whether the memory device [300 and 330, Fig 3] is configured in a first state [1104 and 1106, Fig 11; The unmanaged state is a first state where the host enables background operations to manage spare blocks] and supports enablement and disablement of background operations [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062, 0074 – 0077, and 0091; The status information sent to the host indicates the memory device is enabled to perform certain operations such as a block copy and remapping, returning a block as a spare, manage read/write failures, wear leveling, data relocation, or read scrubbing since the status information causes the host to enable or disable those functions in the memory] or a second state not supporting enablement and disablement of background operations [1108 and 1110, Fig 11; Paragraphs 0062, 0074 – 0077, and 0091; The fully managed spare block mode is a second state where the host is not in control of enabling spare block background operations, the controller is];
wherein the memory device [300 and 330, Fig 3] is configured to be enabled or disabled for the background operations via at least one other register [3110, Fig 13A; The command register stores the commands regarding management operations such as wear leveling and other commands. The memory is not enabled to perform a specific command until the specific command is received 3110] of the number of registers [3110, 3080, 3140, 3150 fig 13A; 3570, Fig 13C] and based on the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; The status information indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed and appropriate commands are sent from the host], wherein the memory device [300 and 330, Fig 3] is either enabled to allow the memory device [300 and 330, Fig 3] to initiate the background operations independent of an external host [1108 and 1110, Fig 11; Paragraphs 0062, 0074 – 0077, and 0091; The fully managed spare block mode is a second state where the host is not in control of enabling spare block background operations, the controller is] or disabled to prohibit the memory device [300 and 330, Fig 3] from initiating the background operations [Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing. When the host is in control the memory is prohibited from initiating the background operations until the host sends commands telling the memory which background operations to perform which then enables the background operations to be initiated by the memory based on the signals from the host].
Regarding claim 10, Selinger teaches the number of registers [3110, 3080, 3140, 3150 fig 13A; 3570, Fig 13C] include one or more of a status register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330], an enablement register, or a time register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; Register 3570 stores information indicating operations need to be started in the future to the host].
Regarding claim 11, Selinger teaches the status register [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] includes one or more bits to be read by a host [120, Fig 1] to determine the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; The status information indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3].
Regarding claim 12, Selinger teaches the status register stores data indicative of enablement of background operations [3570, Fig 13C; Paragraphs 0062, 0074 – 0077, 0104 and 0120 – 0121; The status register is part of 300 and 330 and stores information indicative of what background operations need to be performed].
Regarding claim 13, Selinger teaches time register stores data indicative of a time period associated with the background operations [3570, Fig 13C; Paragraphs 0062, 0074 – 0077, 0104 and 0120 – 0121; Register 3570 stores information indicating background operations need to be started in the future by the host when the that status information indicates the operations are needed such as wear leveling].
Regarding claim 14, Selinger teaches the background operations include one or more of wear leveling [Paragraphs 0062 and 0074 – 0077; Wear leveling is listed as an operation], data collection [Paragraphs 0062 and 0074 – 0077; Relocating data from a bad area to a new area is listed which is a form of collecting data from one area to another area], and block erasing [Paragraphs 0062 and 0073 – 0077; The erasing operations can be left to the host to perform].
Regarding claim 15, Selinger teaches wherein the controller [300, Fig 3] is configured to at least one of:
initiate a background operation in response to a command from the host [120, Fig 1; Paragraphs 0062, 0074 – 0077; The background operations are performed by the controller in response to the host sending commands to the controller to perform the background operations]; or
terminate a background operation in response to receipt of another command from the host.
Regarding claim 16, Selinger teaches determining, via a host [120, Fig 1] in communication with a memory device [300 and 330, Fig 3], a background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077; The status information indicates to the host that the status of a background operation is that the background operation needs to be performed or not performed] of the memory device [300 and 330, Fig 3] indicative of whether the memory device [300 and 330, Fig 3] is configured in a first state [1104 and 1106, Fig 11; The unmanaged state is a first state where the host enables background operations to manage spare blocks] wherein background operations of the memory device [300 and 330, Fig 3] is configured to be enabled or disabled via the host [120, Fig 1; 814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062, 0074 – 0077, and 0091; The status information sent to the host indicates the memory device is enabled to perform certain operations such as a block copy and remapping, returning a block as a spare, manage read/write failures, wear leveling, data relocation, or read scrubbing since the status information causes the host to enable or disable those functions in the memory] or a second state wherein the background operations of the memory device are not configured to be enabled or disabled via the host [1108 and 1110, Fig 11; Paragraphs 0062, 0074 – 0077, and 0091; The fully managed spare block mode is a second state where the host is not in control of enabling spare block background operations, the controller is]; and
enabling or disabling, via the host [120, Fig 1] and based on the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10] of the memory device [300 and 330, Fig 3], the background operations [Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing] to be performed via the memory device [300 and 330, Fig 3; Paragraphs 0062 and 0074 – 0077; Based on the status information the host determines to enable the background operations], wherein enabling the background operations allows the memory device [300 and 330, Fig 3] to initiate the background operations independent of the host [1108 and 1110, Fig 11; Paragraphs 0062, 0074 – 0077, and 0091; The fully managed spare block mode is a second state where the host is not in control of enabling spare block background operations, the controller is] and disabling the background operations prohibits the memory device [300 and 330, Fig 3] from initiating the background operations [Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing. When the background operations are not needed or completed the host and/or memory device is prohibited from initiating the background operations until the background operations are needed to be performed]
Regarding claim 17, Selinger teaches determining the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077] comprises determining the background operation status [814, Fig 8C; 814’, Fig 8D; 900, Fig 9; 1012, Fig 10; Paragraphs 0062 and 0074 – 0077] via one or more bits stored [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] in one or more registers [3570, Fig 13C; Paragraphs 0104 and 0120 – 0121; The status register is part of 300 and 330] of the memory device [300 and 330, Fig 3].
Regarding claim 18, Selinger teaches enabling or disabling the background operations comprises enabling or disabling the background operations [Paragraphs 0062 and 0074 – 0077; The background operations include wear leveling, data relocation, or read scrubbing] via one or more bits [3110, Fig 13A; Paragraphs 0104 – 0108; The host sets bits in the commands register based on the command the host sends to the memory device] stored on the memory device [300 and 330, Fig 3].
Regarding claim 19, Selinger teaches initiating a background operation on the memory device in response to a command from the host [120, Fig 1; Paragraphs 0062 and 0073 – 0077; The host sends commands related to background operations including wear leveling, data relocation, or read scrubbing].
Regarding claim 20, Selinger teaches terminating a background operation on the memory [300 and 330, Fig 3] device in response to receipt of a command from the host [120, Fig 1; Paragraphs 0062 and 0073 – 0077; The host sends commands related to background operations including wear leveling, data relocation, or read scrubbing. The wear leveling, data relocation, and read scrubbing background operations are started and terminated due to the command that initially started the operation. An operation cannot be terminated until it is started showing the command that starts an operation also is responsive for terminating the command].
Response to Arguments
Applicant's arguments filed 01/22/2026 have been fully considered but they are not persuasive.
The applicant argues on page 9 regarding claim 1 that Selinger fails to teach the amended limitation of background operations are enabled to allow the memory device to initiate the background operation independent of the host. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The rejections above have been updated in light of the new amendments to the claims. Selinger teaches in figure 11 the system runs under 3 different modes including unmanaged, fully managed spare block, and split management. In the fully managed spare block mode the memory device and associated controller initiates background operations without the host being involved.
The applicant argues on page 9 regarding claim 1 that Selinger fails to disclose the host determining whether the memory device supports being configured in a first mode where the memory device is allowed to initiate automatic background operation and a second mode wherein the memory device is not allowed to initiate background operations. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The claims fail to disclose what the applicant argues the claims disclose. The amended claims disclose a host determining a background status of the memory device indicative if the memory device is in a first state or a second state. That is not the same as the host determining if the memory device supports being configured in a first or second mode. The claims require the host to determine a mode among two different mode not if the memory supports two modes. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., host determining if a memory device supports a first and second mode) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The applicant argues on pages 9 – 10 that the remaining independent claims contain similar limitations argued allowable above and the dependent claims are dependent on argued allowable base claims. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding claim 1 detailing how Selinger teaches the amended limitations. The rejections of the remaining independent claims are maintained based in part on the rejection of independent claim 1. The rejections of the dependent claims are maintained base in part on the rejections of the independent claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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