DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 29 May 2024 complies with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement.
Drawings
The drawings submitted have been reviewed and determined to facilitate understanding of the invention. The drawings are accepted as submitted.
Election/Restrictions
Applicant’s election without traverse of Invention I, Claims 1-10 and 17-20 in the reply filed on 12 May 2026 is acknowledged.
Claims 11-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication US 2007/0223935 A1 to Asai et al. (“US1”).
Regarding Claim 17, US1 describes a semiconductor optical waveguide (see Figs 4-5), comprising:
a semiconductor substrate (421, 521), defining:
opposing top and bottom surfaces (see Figs 4-5); and
an optical through-substrate via (optical TSV) (442, 542) extending substantially perpendicular to the top and bottom surfaces; and
a waveguide optical circuit (450, 550) on the semiconductor substrate and optically connected to the optical TSV.
Regarding Claim 19, US1 describes the waveguide optical circuit comprising:
a first optical waveguide (450a, 450c, 550a, 550c) on a first side of the semiconductor substrate and optically connected to the optical TSV; and
a second optical waveguide (450b, 450d, 550b, 550d) on an opposing second side of the semiconductor substrate and optically connected to the optical TSV, wherein
the optical TSV optically connects the first and second optical waveguides together (see Figs 4-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6, 8, 10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US1.
Regarding Claim 1, US1 describes co-packaged optics (CPO) integrated circuit chip (see Figs 4-5), comprising:
a semiconductor substrate (421, 521), defining:
opposing top and bottom surfaces (see Figs 4-5); and
an optical through-substrate via (optical TSV) (442, 542) extending substantially perpendicular to the top and bottom surfaces; and
a waveguide optical circuit (450, 550) on the semiconductor substrate and optically connected to the optical TSV; and
an electronic circuit on the semiconductor substrate (via 437, 537; see [0232], [0246], [0462], [0621]-[0622]).
US1 does not specifically describe the electronic circuits as computer processor based electronic circuits. However, it is well-known in the art to use computer processor based electronic circuits for driver ICs, which are described by US1 as on the semiconductor substrate see [0621]-[0622]). Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use such a well-known computer processor based electronic circuit for the driver circuit of US1. The motivation for doing so would have been to make a simple substitution of one known element for another to obtain predictable results.
Regarding Claim 2, US1 describes the optical TSV comprising a post (see Figs 4-5, [0098]-[0101], [0227]-[0228]). US1 does not describe the material of the post as silicon-based. Silicon-based materials are well-known in the art for use in forming components allowing for the transmission of optical signals. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to form the post of the optical TSV of US1 from a silicon-based material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. The motivation for doing so would have been to make a simple substitution of one known material for another to obtain predictable results.
Regarding Claim 3, US1 describes the optical TSV comprising:
a longitudinal height defined by a distance that the optical TSV extends substantially perpendicular to the top and bottom surfaces (see Figs 4-5); and
a lateral width defined by a distance that the optical TSV extends substantially parallel to the top and bottom surfaces (see Figs 4-5),
wherein the lateral width is less than the longitudinal height (see Figs 4-5).
Regarding Claim 4, US1 describes the waveguide optical circuit comprising:
a first optical waveguide (450a, 450c, 550a, 550c) on the semiconductor substrate and optically connected to the optical TSV; and
a second optical waveguide (450b, 450d, 550b, 550d) on the semiconductor substrate and optically connected to the optical TSV, wherein
the optical TSV optically connects the first and second optical waveguides together (see Figs 4-5).
Regarding Claim 6, US1 describes he first and second optical waveguides on opposing sides of the semiconductor substrate (see Figs 4-5).
Regarding Claim 8, US1 describes at least one of the first and second optical waveguides forming a reflecting surface in optical (453, 553) communication with the optical TSV.
Regarding Claim 10, US1 describes the optical TSV defining an annularly-shaped cross section (see Figs 4-5).
The limitations of Claim 18 are substantially similar to the limitations of Claims 2, 3, and 10. Therefore, Claim 18 is obvious in view of US1 for substantially the same reasoning as those claims.
Allowable Subject Matter
Claims 5, 7, 9, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5 and 20 describe:
a third optical waveguide on the semiconductor substrate and optically connected to the optical TSV; and
a fourth optical waveguide on the semiconductor substrate and optically connected to the optical TSV,
wherein the optical TSV optically connects the third and fourth optical waveguides together.
Claim 7 describes at least one of the first and second optical waveguides defining a loop in an optical ring resonator device.
These limitations represent subject matter not described or reasonably suggested, in conjunction with the further limitations of the present claims, by the prior art of record.
Claim 9 depends from Claim 5 and therefore contain at least the same allowable subject matter.
Conclusion
The prior art cited in the attached form PTO-892 are made of record and considered pertinent to applicant's disclosure. The cited prior art describes various optical waveguide structures including optical through-substrate vias.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY RAHLL whose telephone number is (571)272-2356. The examiner can normally be reached M-F 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERRY RAHLL/ Primary Examiner, Art Unit 2874