Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/21/26 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant argues: “The gate terminals of transistors 202 and 204, which are coupled to each other, are coupled to the drain terminal of the FET 112. As Ramachandran does not disclose "a third FET, wherein a gate terminal of the third FET is coupled to the gate terminal of the first FET and the gate terminal of the second FET," Ramachandran does not disclose that "a first current path terminal of the third FET is coupled to the second current path terminal of the current measurement power FET”.
Examiner respectfully disagrees. The claim limitation does not disclose that the gate terminal of the third FET is directly coupled to the gate terminal of the first and second FET. All of the FETs disclosed in Ramachandran are connected to each other and are therefore “coupled” since the broadest reasonable interpretation of the term “coupled” is defined as “linked or connected”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7-12, 14, 15, 17, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramachandran et al., US 11,243,235
Regarding claim 1, Ramachandran discloses a device for measuring a power current to be supplied by a main power field effect transistor (FET), the device comprising: a current measurement power FET comprising a first current path terminal couplable to a first current path terminal of the main power FET (Fig. 1; FET 104 and 106); and a first FET and a second FET, wherein a gate terminal of the first FET is electrically coupled to a gate terminal of the second FET (Fig. 1; FET 110, 112), wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measurement power FET, or wherein a first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET (Fig. 1; FETs 110, 112, 104, 106 are all connected to each other and are therefore coupled; alternatively, FETs 202, 204 in Fig. 2 also can be considered to be a first and second FET as they are also connected to FETs 104, 106), a second current path terminal of the main power FET, a voltage source, or a load external to the device, and a second current path terminal of the first FET is electrically coupled to a second current path terminal of the second FET (Fig. 1; FETs 110, 112, 104, 106 and load 102 are all connected to each other and are therefore coupled to the multiple current paths); and a third FET, wherein a gate terminal of the third FET is coupled to the gate terminal of the first FET and the gate terminal of the second FET, and wherein a first current path terminal of the third FET is coupled to the first current path terminal of the first FET or the second current path terminal of the main power FET (Fig. 2; FET 202 or 204 are connected to the fets 110, 112, 104, 106).
Regarding claim 5, Ramachandran discloses further comprising a comparator having a first input couplable to the second current path terminal of the main power FET, a second input of the comparator couplable to the second current path terminal of the current measurement power FET, and an output of the comparator couplable to the gate terminal of the first FET and the gate terminal of the second FET (Fig. 1).
Regarding claim 7, Ramachandran discloses a fourth FET, wherein a first current path terminal of the fourth FET is coupled to the second current path terminal of the current measurement power FET, and a second current path terminal of the fourth FET is coupled to the first current path terminal of the first FET; and a comparator having a first input coupled to the second current path terminal of the current measurement power FET, a second input of the comparator couplable to the second current path terminal of the main power FET, and an output of the comparator coupled to a gate terminal of the fourth FET (Fig. 2).
Regarding claim 8, Ramachandran discloses wherein the first FET and the second FET are arranged as a current mirror (Fig. 2; 202, 204).
Regarding claim 9, Ramachandran teaches wherein the first FET and the second FET are P-type, wherein the gate terminal of the first FET and the gate terminal of the second FET are coupled to the second current path terminal of the first FET, and wherein the first current path terminal of the second FET is coupled to the first current path terminal of the first FET (Fig. 2; 202, 204 are p-type).
Regarding claim 10, Ramachandran discloses wherein the first FET and the second FET are N-type, wherein the gate terminal of the first FET and the gate terminal of the second FET are coupled to the first current path terminal of the first FET, and wherein the second current path terminal of the first FET and the second current path terminal of the second FET are electrically coupled (Fig. 1; Col. 3 lines 60-Col. 4 lines 15).
Regarding claim 11, Ramachandran teaches a power control circuit for controlling an electrical load, the power control circuit comprising: a main power field effect transistor (FET) comprising a first current path terminal couplable to an electrical power source(Fig. 1; FET 104 to source 108); a second current path terminal of the main FET couplable to a terminal of the electrical load (Fig. 1; load 102); and a measurement circuit configured to measure a power current to be supplied by the main FET, the measurement circuit comprising: a current measurement power FET comprising a first current path terminal couplable to a first current path terminal of the main power FET (Fig. 1; FET 106); and a first FET and a second FET, wherein a gate terminal of the first FET is electrically coupled to a gate terminal of the second FET, wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measurement power FET, or wherein a first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET(Fig. 1; FETs 110, 112, 104, 106 are all connected to each other and are therefore coupled; alternatively, FETs 202, 204 in Fig. 2 also can be considered to be a first and second FET as they are also connected to FETs 104, 106), a second current path terminal of the main power FET, a voltage source, or the electrical load, and a second current path terminal of the first FET electrically coupled to a second current path terminal of the second FET(Fig. 1; FETs 110, 112, 104, 106 and load 102 are all connected to each other and are therefore coupled to the multiple current paths); and wherein a gate terminal of a third FET is coupled to the gate terminal of the first FET and the gate terminal of the second FET, and wherein a first current path terminal of the third FET is coupled to the first current path terminal of the first FET or the second current path terminal of the main power FET (Fig. 2; FET 202 or 204 are connected to the fets 110, 112, 104, 106).
Regarding claim 12, Ramachandran teaches wherein the main power FET and the current measurement power FET are of a same conductivity type (Col. 3 lines 30-50).
Regarding claim 14, Ramachandran teaches wherein the measurement circuit further comprises a comparator having a first input couplable to the second current path terminal of the main power FET, a second input of the comparator couplable to the second current path terminal of the current measurement power FET, and an output of the comparator couplable to the gate terminal of the first FET and the gate terminal of the second FET (Fig. 1; comparator 114).
Regarding claim 15, Ramachandran teaches a method to measure a power current to be supplied by a main power field effect transistor (FET) in a device, the method comprising: receiving a control signal at a gate terminal of a current measurement power FET ((Fig. 1; FET 106), the gate terminal of the current measurement power FET is coupled to a gate terminal of the main FET (Fig. 1; FET 104 and 106), and a first current path terminal of the current measurement power FET coupled to a first current path terminal of the main power FET (Fig. 1; FET 104 and 106, as shown are connected); and regulating, by a comparator, a first potential at a second terminal of the current measurement power FET to equal a second potential at a second terminal of the main FET (Fig. 1; amplifier 114; Col. 3 lines 60- Col. 4 lines 15 ), wherein a gate terminal of a first FET is electrically coupled to a gate terminal of a second FET, wherein a first current path terminal of the first FET is coupled to a second current path terminal of the current measurement power FET, or wherein a first current path terminal of the second FET is coupled to the first current path terminal of the current measurement power FET (Fig. 1; FETs 110, 112, 104, 106 are all connected to each other and are therefore coupled; alternatively, FETs 202, 204 in Fig. 2 also can be considered to be a first and second FET as they are also connected to FETs 104, 106), a second current path terminal of the main power FET, a voltage source, or an external electrical load, and a second current path terminal of the first FET electrically coupled to a second current path terminal of the second FET(Fig. 1; FETs 110, 112, 104, 106 and load 102 are all connected to each other and are therefore coupled to the multiple current paths); and wherein a gate terminal of a third FET is coupled to the gate terminal of the first FET and the gate terminal of the second FET, and wherein a first current path terminal of the third FET is coupled to the first current path terminal of the first FET or the second current path terminal of the main power FET (Fig. 2; FET 202 or 204 are connected to the fets 110, 112, 104, 106).
Regarding claim 17, Ramachandran teaches wherein the comparator includes a first input coupled to the second current path terminal of the main power FET, a second input of the comparator is coupled to the second current path terminal of the current measurement power FET, and an output of the comparator is coupled to the gate terminal of the first FET and the gate terminal of the second FET (Fig. 1; as shown, all elements are connected).
Regarding claim 20, Ramachandran teaches wherein the first FET and the second FET are P-type, wherein the gate terminal of the first FET and the gate terminal of the second FET are coupled to the second current path terminal of the first FET, and wherein the first current path terminal of the second FET is coupled to the first current path terminal of the first FET, or wherein the first FET and the second FET are N-type, wherein the gate terminal of the first FET and the gate terminal of the second FET are coupled to the first current path terminal of the first FET, and wherein the second current path terminal of the first FET and the second current path terminal of the second FET are electrically coupled (Fig. 1; Col. 3 lines 60-Col. 4 lines 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2, 4, 13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al., US 11,243,235 in view of Tanaka, US 6339318
Regarding claim 2, Ramachandran is silent in wherein a semiconductor surface of the current measurement power FET and channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of the current measurement power FET. Tanaka teaches channel widths of a first FET and a second FET are such that a ratio between a charging current to be supplied at a current path terminal of a main power FET and an output current to be supplied at a second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of a current measurement power FET (Col. 4 lines 50-55; channel widths of the MOSFETs are differentiated). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tanaka into Ramachandran for the benefit of providing a differential circuit design having offsets (Col. 4 lines 50-60).
Regarding claim 4, Ramachandran is silent in wherein channel widths of the first FET and the second FET are different. Tanaka teaches wherein channel widths of a first and second FET are different (Col. 4 lines 50-55; channel widths of the MOSFETs are differentiated). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tanaka into Ramachandran for the benefit of providing a differential circuit design having offsets (Col. 4 lines 50-60).
Regarding claim 13, Ramachandran is silent in wherein a semiconductor surface of the current measurement power FET and channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of the current measurement power FET. Tanaka teaches channel widths of a first FET and a second FET are such that a ratio between a charging current to be supplied at a current path terminal of a main power FET and an output current to be supplied at a second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of a current measurement power FET (Col. 4 lines 50-55; channel widths of the MOSFETs are differentiated). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tanaka into Ramachandran for the benefit of providing a differential circuit design having offsets (Col. 4 lines 50-60).
Regarding claim 16, Ramachandran is silent in wherein a semiconductor surface of the current measurement power FET and channel widths of the first FET and the second FET are such that a ratio between a charging current to be supplied at the second current path terminal of the main power FET and an output current to be supplied at the second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of the current measurement power FET. Tanaka teaches channel widths of a first FET and a second FET are such that a ratio between a charging current to be supplied at a current path terminal of a main power FET and an output current to be supplied at a second current path terminal of the first FET differs from a ratio between a semiconductor surface of the main power FET and the semiconductor surface of a current measurement power FET (Col. 4 lines 50-55; channel widths of the MOSFETs are differentiated). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Tanaka into Ramachandran for the benefit of providing a differential circuit design having offsets (Col. 4 lines 50-60).
Claim 3, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al., US 11,243,235 in view of Nomoto, US 6185488
Regarding claim 3, Ramachandran teaches wherein the first FET and second FET are of a MOSFET type. Ramachandran is silent in wherein the current measurement power FET is of a vertical double-diffused metal-oxide-semiconductor FET (VDMOSFET) type. Nomoto teaches wherein a power FET is of a vertical double-diffused metal-oxide-semiconductor FET (VDMOSFET) type (Col. 7 lines 8-12). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to substitute the VDMOS as taught by Nomoto into Ramachandran since the substitution would produce the predictable result of a switching device to connect or disconnect a power supply.
Regarding claim 19, Ramachandran is silent in wherein the current measurement power FET is of a vertical double-diffused metal-oxide-semiconductor FET (VDMOSFET) type, and wherein the first FET and second FET are of a MOSFET type. Nomoto teaches wherein a power FET is of a vertical double-diffused metal-oxide-semiconductor FET (VDMOSFET) type (Col. 7 lines 8-12). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to substitute the VDMOS as taught by Nomoto into Ramachandran since the substitution would produce the predictable result of a switching device to connect or disconnect a power supply.
Allowable Subject Matter
Claims 21, 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 21, prior art does not disclose or suggest: “ wherein a second current path terminal of the third FET is configured to independently provide a third sense current proportional to the power current, the third sense current being independent from a first sense current provided at the second current path terminal of the first FET and a second sense current provided at the second current path terminal of the second FET” in combination with all the limitations of claim 21.
Regarding claim 22, prior art does not disclose or suggest: “wherein a second current path terminal of the third FET is configured to independently provide a third sense current proportional to the power current, the third sense current being independent from a first sense current provided at the second current path terminal of the first FET and a second sense current provided at the second current path terminal of the second FET” in combination with all the limitations of claim 22.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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