DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-13, 15-24, and 26-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sekine (US 2019/0065116).
In regards to claims 1 and 12, Sekine teaches a memory storage device, comprising:
a connection interface unit, configured to couple to a host system (“The interface unit 13 performs front-end communication with the interface unit 15 of the host device 2”, paragraph 0047);
a rewritable non-volatile memory module (“In this embodiment, the nonvolatile memory 4_1 to 4_n are, for example, NAND type flash memory.”, paragraph 0027);
a memory control circuit unit (Controller 3, figure 1), coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to:
obtain device status information of the memory storage device, wherein the device status information reflects whether the memory storage device is performing a default operation (“The measurement unit 16 or the setting unit 18 measures or sets, for example, the bandwidth consumption amount D20 of the background job executed by the NAND control circuit 7 for the nonvolatile memory 4_1 to 4_n.”, paragraph 0144); and
adjust a connection interface standard used by the connection interface unit from a first connection interface standard to a second connection interface standard according to the device status information, wherein the first connection interface standard is different from the second connection interface standard (“The detection unit 9B obtains a value “V14−V15=V16 gigabytes/second” which is a subtraction of the bandwidth consumption amount D20 ‘V15 gigabytes/second’ of the background job from the maximum back-end transfer rate D19 ‘V14 gigabytes/second’. Then, for example, the detection unit 9B detects the maximum front-end transfer rate D21 ‘V16 gigabytes/second’ based on the obtained value ‘V16 gigabytes/second’. The determination unit 12B determines the generation and link width Dgl5 of the communication interface 5 for ‘V16 gigabytes/second’.”, paragraphs 0147-0148; “In this embodiment, a communication interface 5 used for the front-end communication between the storage device 1 and the host device 2 is described as complying with the PCI Express® standard, but other communication interfaces may be used.”, paragraph 0028; “In this embodiment, Gen1, Gen2 and Gen3 are used as the generation of the communication interface 5, but other generations of the communication interface 5 may be used.”, paragraph 0030),
wherein adjusting the connection interface standard used by the connection interface unit from the first connection interface standard to the second connection interface standard by the memory control unit comprises:
in response to the memory storage device performing the default operation generating an expected data transfer volume per unit time between the memory storage device and the host system (“The detection unit 9B obtains a value “V14−V15=V16 gigabytes/second” which is a subtraction of the bandwidth consumption amount D20 ‘V15 gigabytes/second’ of the background job from the maximum back-end transfer rate D19 ‘V14 gigabytes/second’. Then, for example, the detection unit 9B detects the maximum front-end transfer rate D21 ‘V16 gigabytes/second’ based on the obtained value ‘V16 gigabytes/second’.”, paragraph 0147); and
adjusting the connection interface standard used by the connection interface unit from the first connection interface standard to the second connection interface standard according to the expected data transfer volume per unit time (“The determination unit 12B determines the generation and link width Dgl5 of the communication interface 5 for ‘V16 gigabytes/second’.”, paragraph 0148).
In regards to claim 23, Sekine teaches a memory control circuit unit, for controlling a memory storage device, wherein the memory storage device comprises a connection interface unit, the connection interface unit is configured to couple to a host system, and the memory control circuit unit comprises:
a host interface, configured to couple to the connection interface unit (“The interface unit 13 performs front-end communication with the interface unit 15 of the host device 2”, paragraph 0047);
a memory interface, configured to couple to a rewritable non-volatile memory module (“The storage device 1 is connected with the host device 2 to communicate with each other, and includes a controller 3 and nonvolatile memory 4_1 to 4_n. In this embodiment, the nonvolatile memory 4_1 to 4_n are, for example, NAND type flash memory.”, paragraphs 0026-0027); and
a memory management circuit (Controller 3, figure 1), coupled to the host interface and the memory interface,
wherein the memory management circuit is configured to:
obtain device status information of the memory storage device, wherein the device status information reflects whether the memory storage device is performing a default operation (“The measurement unit 16 or the setting unit 18 measures or sets, for example, the bandwidth consumption amount D20 of the background job executed by the NAND control circuit 7 for the nonvolatile memory 4_1 to 4_n.”, paragraph 0144); and
adjust a connection interface standard used by the connection interface unit from a first connection interface standard to a second connection interface standard according to the device status information, wherein the first connection interface standard is different from the second connection interface standard (“The detection unit 9B obtains a value “V14−V15=V16 gigabytes/second” which is a subtraction of the bandwidth consumption amount D20 ‘V15 gigabytes/second’ of the background job from the maximum back-end transfer rate D19 ‘V14 gigabytes/second’. Then, for example, the detection unit 9B detects the maximum front-end transfer rate D21 ‘V16 gigabytes/second’ based on the obtained value ‘V16 gigabytes/second’. The determination unit 12B determines the generation and link width Dgl5 of the communication interface 5 for ‘V16 gigabytes/second’.”, paragraphs 0147-0148; “In this embodiment, a communication interface 5 used for the front-end communication between the storage device 1 and the host device 2 is described as complying with the PCI Express® standard, but other communication interfaces may be used.”, paragraph 0028; “In this embodiment, Gen1, Gen2 and Gen3 are used as the generation of the communication interface 5, but other generations of the communication interface 5 may be used.”, paragraph 0030),
wherein adjusting the connection interface standard used by the connection interface unit from the first connection interface standard to the second connection interface standard by the memory management circuit comprises:
in response to the memory storage device performing the default operation, generating an expected data transfer volume per unit time between the memory storage device and the host system (“The detection unit 9B obtains a value “V14−V15=V16 gigabytes/second” which is a subtraction of the bandwidth consumption amount D20 ‘V15 gigabytes/second’ of the background job from the maximum back-end transfer rate D19 ‘V14 gigabytes/second’. Then, for example, the detection unit 9B detects the maximum front-end transfer rate D21 ‘V16 gigabytes/second’ based on the obtained value ‘V16 gigabytes/second’.”, paragraph 0147); and
adjusting the connection interface standard used by the connection interface unit from the first connection interface standard to the second connection interface standard according to the expected data transfer volume per unit time (“The determination unit 12B determines the generation and link width Dgl5 of the communication interface 5 for ‘V16 gigabytes/second’.”, paragraph 0148).
In regards to claims 2, 13, and 24, Sekine further teaches that the default operation comprises at least one of a garbage collection operation, a wear leveling operation, a device self-test operation, and an error handle operation (“Examples of the background job may be patrol and refresh, or garbage collection, etc.”, paragraph 0145).
In regards to claims 4, 15, and 26, Sekine further teaches that generating the expected data transfer volume per unit time between the memory storage device and the host system by the memory control circuit unit comprises:
obtaining the expected data transfer volume per unit time corresponding to the default operation from a comparison table (“FIG. 2 is a diagram illustrating an example of a data structure for the setting candidate data 14 used in the present embodiment. In the setting candidate data 14, the generations Gen1 to Gen3 and the link widths x1, x2 and x4 are associated with various back-end transfer rates. Other generations and link widths may be associated with the back-end transfer rates.”, paragraphs 0049-0050; See also figure 2).
In regards to claims 5, 16, and 27, Sekine further teaches that the device status information further comprises a current transfer rate of the memory storage device (“The measurement unit 16 or the setting unit 18 measures or sets, for example, the bandwidth consumption amount D20 of the background job executed by the NAND control circuit 7 for the nonvolatile memory 4_1 to 4_n.”, paragraph 0144), and generating the expected data transfer volume per unit time between the memory storage device and the host system by the memory control circuit unit comprises:
obtaining the expected data transfer volume per unit time according to the current transfer rate based on the default operation (“The detection unit 9B obtains a value “V14−V15=V16 gigabytes/second” which is a subtraction of the bandwidth consumption amount D20 ‘V15 gigabytes/second’ of the background job from the maximum back-end transfer rate D19 ‘V14 gigabytes/second’. Then, for example, the detection unit 9B detects the maximum front-end transfer rate D21 ‘V16 gigabytes/second’ based on the obtained value ‘V16 gigabytes/second’.”, paragraph 0147).
In regards to claims 6, 17, and 28, Sekine further teaches that the memory control circuit unit is further configured to:
in response to completing the default operation (“In step S305, when the controller 3 continues the processing, the controller 3 returns to step S302.”, paragraph 0065), restore the connection interface standard used by the connection interface unit from the second connection interface standard to the first connection interface standard (“In step S303, the determination unit 12 of the controller 3 determines the generation and link width of the communication interface 5 corresponding to the back-end transfer rate, based on the detected back-end transfer rate and the setting candidate data 14.”, paragraph 0063).
In regards to claims 7, 18, and 29, Sekine further teaches that the memory control circuit unit is further configured to:
in response to completing the default operation, adjust the connection interface standard used by the connection interface unit from the second connection interface standard to a third connection interface standard (“In step S303, the determination unit 12 of the controller 3 determines the generation and link width of the communication interface 5 corresponding to the back-end transfer rate, based on the detected back-end transfer rate and the setting candidate data 14.”, paragraph 0063) according to a current temperature of the memory storage device (“In the present embodiment, the back-end throttling set value D16 is information indicating the limitation on the performance to ‘V11%’ in the case of the temperature D15 ‘V10° C.’.”, paragraph 0137) or a number of pending commands, wherein the third connection interface standard is different from the first connection interface standard and the second connection interface standard (“In this embodiment, Gen1, Gen2 and Gen3 are used as the generation of the communication interface 5, but other generations of the communication interface 5 may be used.”, paragraph 0030).
In regards to claims 8, 19, and 30, Sekine further teaches that the memory control circuit unit is further configured to:
receive a power status protocol from the host system, wherein the power status protocol comprises a default condition for adjusting the connection interface standard used by the connection interface unit and a specified connection interface standard corresponding to the default condition (“The back-end throttling set value D11 can be obtained based on the power consumption mode set value D9 which may be set according to an instruction from the host device 2.”, paragraph 0160); and
in response to the default condition being met, adjust the connection interface standard used by the connection interface unit from the first connection interface standard to the specified connection interface standard, wherein the first connection interface standard is different from the specified connection interface standard (“The determination unit 12B determines the generation and link width Dgl3 of the communication interface 5 for ‘V9 gigabytes/second’.”, paragraph 0134).
In regards to claims 9, 20, and 31, Sekine further teaches that the memory control circuit unit is further configured to:
receive a switching command and a specified connection interface standard from the host system (“The various set values used in this embodiment may be determined, for example, based on an instruction from the host device 2.”, paragraph 0092); and
adjust the connection interface standard used by the connection interface unit from the first connection interface standard to the specified connection interface standard based on the switching command, wherein the first connection interface standard is different from the specified connection interface standard (“In this embodiment, the generation and link width of the communication interface 5 are determined based on various measured values or set values.”, paragraph 0091).
In regards to claims 10, 21, and 32, Sekine further teaches that the connection interface standard used by the connection interface unit comprises at least two of N generations of PCI Express standards, wherein N is a positive integer greater than 0 (“In this embodiment, a communication interface 5 used for the front-end communication between the storage device 1 and the host device 2 is described as complying with the PCI Express® standard, but other communication interfaces may be used.”, paragraph 0028; “In this embodiment, Gen1, Gen2 and Gen3 are used as the generation of the communication interface 5, but other generations of the communication interface 5 may be used.”, paragraph 0030).
In regards to claims 11, 22, and 33, Sekine further teaches that in response to the connection interface unit using the first connection interface standard, the memory storage device has a first data transfer volume per unit time upper limit (“More specifically, in the setting candidate data 14A, the generation Gen1 and the link width x1 are associated with the low front-end transfer rate, the generation Gen2 and the link width x2 are associated with the medium front-end transfer rate, and the generation Gen3 and the link width x4 are associated with the high front-end transfer rate.”, paragraph 0085),
in response to the connection interface unit using the second connection interface standard, the memory storage device has a second data transfer volume per unit time upper limit, wherein the first data transfer volume per unit time upper limit is different from the second data transfer volume per unit time upper limit (id.).
Response to Arguments
Applicant's arguments filed 17 November 2025 have been fully considered but they are not persuasive.
First, Sekine does adjust the PCIe generation based on the calculated bandwidth (See paragraph 0148). Second, claim 1 does not prohibit measuring the bandwidth consumption but does include generating an expected bandwidth. Sekine’s V16 is an example of a generated expected bandwidth. V16 is a calculated value, not a measured value (See paragraph 0147). Since Sekine uses a previously measured value V15 to determine the front-end transfer rate V16, the front-end transfer rate is not a measured value but an expected value. Sekine notes this in a similar context stating “Then, for example, the detection unit 9B estimates the maximum front-end transfer rate D8 ‘V6 Gigabytes/second’ based on the maximum back-end transfer rate D7.” (paragraph 0124)
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 12 January 2026