CTNF 18/678,025 CTNF 79300 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ahlgren et al (US 2005/0242373 A1) . Regarding claim 1, Ahlgren et al discloses a device comprising a bipolar transistor (Figure 3, paragraph 0071), the bipolar transistor comprising: a collector region (Figure 3, reference 18), a base region (Figure 3, reference 22), and an emitter region (Figure 3, reference 36); a first metallization (Figure 3, reference 45) at an upper surface of the emitter region (Figure 3, reference 36); and a connection element (Figure 3, reference 60) coupled to the first metallization (Figure 3, reference 45) and having dimensions, in a plane of an interface between the first metallization (Figure 3, reference 45) and the connection element (Figure 3, reference 60), greater than dimensions of the first metallization. Regarding claim 2, Ahlgren et al discloses wherein a distance between opposite walls of the connection element (Figure 3, reference 60 left and right ends) is greater than a distance between opposite walls of the first metallization (Figure 3, reference 45 left and right ends) in a same direction. Regarding claim 3, Ahlgren et al discloses wherein an upper surface of the first metallization (Figure 3, reference 45) is entirely covered by, and in contact with, the connection element (Figure 3, reference 60). Regarding claim 4, Ahlgren et al discloses wherein the transistor is covered with a first insulating layer (Figure 3, reference 56), and wherein the connection element (Figure 3, reference 60) crosses through the first insulating layer (Figure 3, reference 56) to reach the first metallization (Figure 3, reference 45). Regarding claim 5, Ahlgren et al discloses wherein the bipolar transistor further comprises: a second metallization (Figure 3, reference 44) at an upper surface of the base region (Figure 3, references 22 and 27); and a first spacer (Figure 3, reference 54) that at least partially covers the second metallization (Figure 3, reference 44). Regarding claim 6, Ahlgren et al discloses wherein the first spacer (Figure 3, reference 54) surrounds the emitter region (Figure 3, reference 36). Regarding claim 7, Ahlgren et al discloses wherein the transistor is covered with a first insulating layer (Figure 3, reference 56), and wherein the device comprises a conductive contact (Figure 3, reference 62) crossing through the first insulating layer (Figure 3, reference 56) to reach the second metallization (Figure 3, reference 44 right). Regarding claim 8, Ahlgren et al discloses wherein the conductive contact (Figure 3, reference 62) further crosses through the first spacer (Figure 3, reference 54). Regarding claim 9, Ahlgren et al discloses wherein a material of the first insulating layer (Figure 3, reference 56) is selectively etchable over a material of the first spacer (Figure 3, reference 54; paragraphs 0058-0060). Regarding claim 10, Ahlgren et al discloses wherein the transistor comprises a second spacer (Figure 3, reference 32) that is at least partially covered by the first spacer (Figure 2, reference 56), and wherein said second spacer (Figure 3, reference 32) does not cover the second metallization (Figure 3, reference 44). Regarding claim 11, Ahlgren et al discloses wherein the bipolar transistor further comprises: a third metallization (Figure 3, reference 46) at an upper surface of the collector region (Figure 3, reference 18); and a third spacer (Figure 3, reference 54 right) that at least partially covers the third metallization (Figure 3, reference 46). Regarding claim 12, Ahlgren et al discloses wherein the third spacer (Figure 3, reference 14) surrounds the base region (Figure 2, reference 22). Regarding claim 13, Ahlgren et al discloses wherein the transistor is covered with a first insulating layer (Figure 3, reference 56), and wherein the device comprises a conductive contact (Figure 3, reference 64) crossing through the first insulating layer (Figure 3, reference 56) to reach the third metallization (Figure 3, reference 46). Regarding claim 14, Ahlgren et al discloses wherein the conductive contact (Figure 3, reference 64) further crosses through the third spacer (Figure 3, reference 54 right). Regarding claim 15, Ahlgren et al discloses wherein a material of the first insulating layer (Figure 3, reference 56) is selectively etchable over a material of the third spacer (Figure 3, reference 54 right; paragraphs 0058-0060). Regarding claim 16, Ahlgren et al discloses wherein the transistor comprises a fourth spacer (Figure 3, reference 14) that is at least partially covered by the third spacer (Figure 3, reference 54 right), and wherein said fourth spacer (Figure 3, reference 14) does not cover the third metallization (Figure 3, reference 46). Regarding claim 17, Ahlgren et al discloses a device comprising a bipolar transistor (Figure 3, paragraph 0071), the bipolar transistor comprising: a collector region (Figure 3, reference 18), a base region (Figure 3, reference 22), and an emitter region (Figure 3, reference 36); a first metallization (Figure 3, reference 45) at an upper surface of the emitter region (Figure 3, reference 36); and a connection element (Figure 3, reference 60) coupled to the first metallization (Figure 3, reference 45) and having dimensions, in a plane of an interface between the first metallization (Figure 3, reference 45) and the connection element (Figure 3, reference 60), greater than dimensions of the first metallization (Figure 3, reference 45); a second metallization (Figure 3, reference 44) at an upper surface of the base region (Figure 3, references 22 and 27); a first spacer (Figure 3, reference 54) that at least partially covers the second metallization (Figure 3, reference 44); wherein the transistor (Figure 3, paragraph 0071) is covered with a first insulating layer (Figure 3, reference 56); wherein the connection element (Figure 3, reference 60) crosses through the first insulating layer (Figure 3, reference 56) to reach the first metallization (Figure 3, reference 45); wherein the device comprises a conductive contact (Figure 3, reference 62) crossing through the first insulating layer (Figure 3, reference 56) to reach the second metallization (Figure 3, reference 44 right); and wherein the conductive contact (Figure 3, reference 62) further crosses through the first spacer (Figure 3, reference 54). Regarding claim 18, Ahlgren et al discloses wherein an upper surface of the first metallization (Figure 3, reference 45) is entirely covered by, and in contact with, the connection element (Figure 3, reference 60). Regarding claim 19, Ahlgren et al discloses wherein the first spacer (Figure 3, reference 54) surrounds the emitter region (Figure 3, reference 36). Regarding claim 20, Ahlgren et al discloses wherein the transistor comprises a second spacer (Figure 3, reference 14) that is at least partially covered by the first spacer (Figure 3, reference 54), and wherein said second spacer (Figure 3, reference 14) does not cover the second metallization (Figure 3, reference 44 right) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Asai et al (6,455,364 B1) discloses a semiconductor device and a method for fabricating the semiconductor device, more particularly, a hetero bipolar transistor, a Bi-CMOS device including the hetero bipolar transistor, and method for fabricating such devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/Primary Examiner, Art Unit 2815 mdh June 15, 2026 Application/Control Number: 18/678,025 Page 2 Art Unit: 2815 Application/Control Number: 18/678,025 Page 3 Art Unit: 2815 Application/Control Number: 18/678,025 Page 4 Art Unit: 2815 Application/Control Number: 18/678,025 Page 5 Art Unit: 2815 Application/Control Number: 18/678,025 Page 6 Art Unit: 2815 Application/Control Number: 18/678,025 Page 7 Art Unit: 2815 Application/Control Number: 18/678,025 Page 8 Art Unit: 2815
Prosecution Insights