Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-19 are pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent 12,033,713. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of U.S. Patent 12,033,713 repeat the features of claims 1-19, therefore anticipate claims 1-19 of the instant application.
Claim 1 (US Application 18/678,072)
Claim 1 (U.S. Patent 12,033,713)
A neural processing unit (NPU) for testing a component during runtime, the NPU comprising:
at least one memory; and
a plurality of processing elements (PEs) which are configured to operate for an operation of an artificial neural network (ANN),
wherein at least one of the at least one memory and the plurality of PEs is selected as a component under test (CUT) and undergoes a test when a collision due to an access to the at least one is not detected.
2. The NPU of claim 1, wherein the plurality of PEs comprise: a first group of PEs and a second group of PEs.
3. The NPU of claim 2, wherein the second group of PEs is configured to perform the operation of the artificial neural network when the test is performed on the first group of PEs.
4. The NPU of claim 1, wherein the at least one memory includes a first group of memory instances and a second group of memory instances.
5. The NPU of claim 4, wherein the second group of memory instances is configured to be used when the test is performed on the first group of memory instances.
6. The NPU of claim 1, wherein the test is a first type of test or a second type of test, wherein the first type of test uses an error detection code, and wherein the second type of test is a read-write test.
7. The NPU of claim 1, wherein each state of the at least one memory and the plurality of PEs is monitored by a component tester.
8. The tester of claim 7, wherein the component tester is included in the NPU or is disposed external to the NPU.
9. The NPU of claim 7, wherein the component tester is configured to: communicate with the at least one memory and the plurality of PEs; select the at least one of the at least one memory and the plurality of PEs as a component under test (CUT), prepare or start a test for the selected CUT, stop the test, based on a detection of a collision due to an access to the at least one, and complete the test, when no collision is detected.
10. The NPU of claim 1, further comprising: a wrapper arranged in correspondence to each of the at least one memory and the plurality of PEs.
A neural processing unit (NPU) for testing a component during runtime, the NPU comprising:
a plurality of functional components including at least one functional component which is configured to operate for an operation of an artificial neural network (ANN), and
another functional component which is selected as a component under test (CUT) and undergoes a function test.
2. The NPU of claim 1, wherein the plurality of functional components include at least one of: at least one memory; at least one controller; and at least one processing element.
3. The NPU of claim 1, wherein the plurality of functional components further include a plurality of memory instances, the plurality of memory instances including a first group of memory instances and a second group of memory instances, and wherein the second group of memory instances is configured to be used when the function test is performed on the first group of memory instances.
4. The NPU of claim 1, wherein, when the CUT includes a plurality of flip-flops and the CUT further undergoes a scan test, the scan test is configured to: form one or more scan chains by connecting the plurality of flip-flops, apply a test input to at least one of the plurality of flip-flops, and acquire a test result from operations of combinational logics of the at least one of the plurality of flip-flops to analyze whether the CUT is defective or normal during runtime.
5. The NPU of claim 1, further comprising a component tester configured to monitor each state of the plurality of functional components.
6. The NPU of claim 1, wherein the plurality of functional components include a first functional component and a second functional component, wherein the first functional component includes a plurality of processing elements (PEs), the plurality of PEs including a first group of PEs and a second group of PEs, and wherein the second group of PEs is configured to perform the operation of the artificial neural network when the function test is performed on the first group of PEs.
Claim 11 (US Application 18/678,072)
Claim 15 (U.S. Patent 12,033,713)
A system comprising:
a neural processing unit (NPU) comprising at least one memory and a plurality of processing elements (PEs) which are configured to operate for an operation of an artificial neural network (ANN),
a component tester configured to:
select at least one of the at least one memory and the plurality of PEs, as a component under test (CUT) and undergo a test when a collision due to an access to the at least one is not detected.
A system comprising:
a neural processing unit (NPU) comprising a plurality of functional components configured to process at least one artificial neural network (ANN) model; and
a component tester configured to:
select at least one functional component, which is detected as an idle state, as a component under test (CUT) among the plurality of functional components, prepare or start a function test for the selected CUT, stop the function test, based on a detection of a collision due to an access to the selected at least one functional component, and complete the function test, when no collision is detected.
Claims 1-20 of U.S. Patent 12,033,713 corresponding in scope to claims 1-19 of the instant application, therefore, anticipate claims 1-19 of the instant application. Therefore, the limitations of claims 1-19 are not patentably distinct from claims 1-20 of U.S. Patent 12,033,713.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 12040040 B2 (KIM et al) teaching system comprising: a neural processing unit (NPU) comprising a plurality of functional components configured to process at least one artificial neural network (ANN) model, wherein the plurality of functional components include a plurality of memory instances; and a component tester configured to: select at least one memory instance as a component under test (CUT) prepare or start a test for the selected CUT, stop the test, based on a detection of a collision due to an access to the selected at least one memory instance, and complete the test, when no collision is detected.
US 20210286693 A1 (ALBEN et al) teaching first testing component corresponding to the component is used to test the component including sub-components of the component when the component is in the low-power state during a first time period. Determination is made on that sub-component of the sub-components is in the low- power state when the component is not in the low-power state during a second time period. The second testing components corresponding to the
US 20180357143 A1 (PANAMBUR et al) teaching Aspects of testing computing devices are described. In an example, a set of logical modules associated with a test case for a component of a computing device being tested is executed using testing information for testing the component. Each logical module in the set of logical modules comprises instructions that, when executed, performs a set of predefined tasks for testing component.
US 10628274 B2 (GULATI et al) teaching self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
US 7577540 B2 (WANG et al) teaching test system for a circuit board , wherein the circuit board has a plurality of cores such that at least one of the plurality of cores is adapted to use a test protocol independent of a communication fabric used in the circuit board. A system-on-chip (SOC) with an embedded test protocol architecture, the SOC comprising at least one embedded core, a communication fabric that connects at least one embedded core, at least one test server; and at least one test client connected to said at least one embedded core and connected to the communication fabric.
Y. He, T. Uezono and Y. Li, "Efficient Functional In-Field Self-Test for Deep Learning Accelerators," 2021 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2021, pp. 93-102.
F. Duarte, J. M. da Silva, J. C. Alves, G. A. Pinho and J. S. Matos, "A processor for testing mixed-signal cores in system-on-chip," 8th Euromicro Conference on Digital System Design (DSD'05), Porto, Portugal, 2005, pp. 184-191.
A. Yazdanbakhsh, J. Park, H. Sharma, P. Lotfi-Kamran and H. Esmaeilzadeh, "Neural acceleration for GPU throughput processors," 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Waikiki, HI, USA, 2015, pp. 482-493.
J. Cullen, "Scan test sequencing hardware for structural test," Proceedings International Test Conference 2001 (Cat. No.01CH37260), Baltimore, MD, USA, 2001, pp. 713-720.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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