CTNF 18/678,191 CTNF 81556 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 5/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 4-7 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. (US Patent Appl. Pub. No. 2022/0068856 A1) in view of Chen et al. (US Patent Appl. Pub. No. 2022/0328467 A1) . [Re claim 1] Chiou discloses the semiconductor package, comprising: an interposer substrate (70) including a substrate (72), a lower protective layer (114) on a lower surface of the substrate, a through-via (80) passing through the substrate and the lower protective layer, a lower pad (132) on a lower surface of the lower protective layer (114), the lower pad (132) in contact with the through-via (80), an interlayer insulating (74 and 78) layer on an upper surface of the substrate, and an interconnection structure (76) in the interlayer insulating layer; a first semiconductor chip (50A) on an upper surface of the interposer substrate, the first semiconductor chip (50A) electrically connected to the interconnection structure and stacked in a direction perpendicular to the upper surface of the interposer substrate; a second semiconductor chip (50B) on the upper surface of the interposer substrate and apart from the first semiconductor chip, the second semiconductor chip (50B) electrically connected to the interconnection structure; an encapsulant (110) on the upper surface of the interposer substrate, the encapsulant covering at least a portion of the first semiconductor chip and at least a portion of the second semiconductor chip, respectively; and connection conductors (136) on the lower surface of the lower protective layer (114), the connection conductors (136) electrically connected to the lower pad (132) (see figure 2-7 and paragraph [0024]-[0050]). However, Chiou does not disclose the device comprising a plurality of first semiconductor chip wherein the plurality of first semiconductor chips includes a lowermost semiconductor chip at a lowest level and upper semiconductor chips stacked on the lowermost semiconductor chip, a thickness of the lowermost semiconductor chip is greater than or equal to a thickness of one of the upper semiconductor chips, and a width of the lowermost semiconductor chip is same as a width of the upper semiconductor chips. Chen discloses the device comprising a plurality of first semiconductor chips (50C) wherein the plurality of first semiconductor chips includes a lowermost semiconductor chip (50C) at a lowest level and upper semiconductor chips (50C) stacked on the lowermost semiconductor chip, a thickness of the lowermost semiconductor chip is greater than or equal to a thickness of one of the upper semiconductor chips, and a width of the lowermost semiconductor chip is same as a width of the upper semiconductor chips (see figure 4 and paragraph [0032]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to form a stack of semiconductor chips in the device of Chiou in order to form a stack of semiconductor chips with high capacitance. [Re claim 4] Chen discloses the semiconductor package wherein each of the upper semiconductor chips (50C) have same thickness (see figure 4). [Re claim 5] Chen discloses the semiconductor package wherein the plurality of first semiconductor chips (50C) includes at least one memory chip (see figure 4 and paragraph [0032]). [Re claim 6] Chen discloses the semiconductor package wherein the second semiconductor chip (50A) includes a logic chip (see figure 4 and paragraph [0032]). [Re claim 7] Chen discloses the semiconductor package wherein a distance from the upper surface of the interposer substrate to uppermost ends of the plurality of first semiconductor chips is 720 μm or less (same as the thickness of the encapsulant 120) (see paragraph [0037]). [Re claim 10] Chen discloses the semiconductor package wherein the plurality of first semiconductor chips (50C) are aligned in the direction perpendicular to the upper surface of the interposer substrate (102) (see figure 13) . 07-21-aia AIA Claim (s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. (US Patent Appl. Pub. No. 2022/0068856 A1) in view of Chen et al. (US Patent Appl. Pub. No. 2022/0328467 A1) and JUNG et al. (US Patent Appl. Pub. No. 2022/0020656 A1) . [Re claim 2] the combined teachings of Chiou and Chen discloses the device as claimed and rejected as claim 1, but Chiou and Chen do not disclose the device wherein uppermost ends of the plurality of first semiconductor chips are coplanar with an uppermost end of the second semiconductor chip. JUNG discloses the semiconductor package wherein uppermost ends of the plurality of first semiconductor chips (320) are coplanar with an uppermost end of the second semiconductor chip (310) (see figure 6 and paragraph [0037]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to the device wherein uppermost ends of the plurality of first semiconductor chips are coplanar with an uppermost end of the second semiconductor chip in the device of Chiou in order to form high-capacity mass storage device . 07-21-aia AIA Claim (s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Patent Appl. Pub. No. 2022/0328467 A1) in view of SEO et al. (US Patent Appl. Pub. No. 2021/0320077 A1) . [Re claim 11] Chen discloses the semiconductor package, comprising: an interposer substrate (102) including a substrate, an interlayer insulating layer 108A-108C) on the substrate, an upper pad (114) on the interlayer insulating layer, and an upper insulating layer (112) on the interlayer insulating layer and surrounding the upper pad; at least one semiconductor chip (50C) on an upper surface of the interposer substrate; and an encapsulant (120) on the upper surface of the interposer substrate and in contact with a side surface of the semiconductor chip, wherein the semiconductor chip includes a first substrate, a first front pad (66) below the first substrate, the first front pad in contact with the upper pad (114), a first front insulating layer (68) surrounding the first front pad, the first front insulating layer (68) in contact with at least a portion of the upper insulating layer (112) (see figure 3-5, 11-12 and paragraphs [0023], [0031], [0033], [0051]-[0053]). However, Chen does not disclose the semiconductor package comprising a first rear insulating layer on the first substrate, and a width of a portion of the upper insulating layer in contact with the first front insulating layer in a horizontal direction is same as a width of the first rear insulating layer in the horizontal direction. SEO discloses the semiconductor package comprising a first rear insulating layer (110) on the first substrate (120), and a width of a portion of the upper insulating layer (160) in contact with the first front insulating layer (130) in a horizontal direction is same as a width of the first rear insulating layer (170) in the horizontal direction (see figure 8A and paragraph [0029]-[0030], [0040]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to form a first rear insulating layer on the first substrate, and a width of a portion of the upper insulating layer in contact with the first front insulating layer in a horizontal direction is same as a width of the first rear insulating layer in the horizontal direction in the device of Chen in order to form high-capacity mass storage device. [Re claim 12] Chen discloses the semiconductor package wherein the at least one semiconductor chip (50C) includes a plurality of semiconductor chips stacked in a direction perpendicular to the upper surface of the interposer substrate (see figure 4). [Re claim 13] Chen discloses the semiconductor package wherein each of the plurality of semiconductor chips (50C) have a same width in the horizontal direction (see figure 4). [Re claim 14] Chen discloses the semiconductor package wherein the plurality of semiconductor chips includes a logic chip at a lowest level (see paragraph [0032]) . 07-21-aia AIA Claim (s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SEO et al. (US Patent Appl. Pub. No. 2021/0320077 A1) in view of JUNG et al. (US Patent Appl. Pub. No. 2022/0020656 A1) . [Re claim 15] SEO discloses the semiconductor package comprising: an interposer substrate (1000); a plurality of first semiconductor chips (100) on the interposer substrate, each of the plurality of first semiconductor chips having a same width in a horizontal direction; conductive bumps (155) between the plurality of first semiconductor chips and electrically connecting each of the plurality of first semiconductor chips to each other; a plurality of adhesive films (160) surrounding at least a portion of the conductive bumps; a second semiconductor chip (900) on the interposer substrate and spaced apart from the plurality of first semiconductor chips (see figure 8A and paragraph [0033], [0040], [0120]). However, SEO does not disclose the semiconductor package comprising: first and second underfill portions on the interposer substrate, the first and second underfill portions respectively covering at least a portion of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip; and an encapsulant covering at least a portion of each of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip. JUNG discloses the semiconductor package comprising: first and second underfill portions (450) on the interposer substrate (202), the first and second underfill portions respectively covering at least a portion of the plurality of first semiconductor chips (320) and at least a portion of the second semiconductor chip (310); and an encapsulant (500) covering at least a portion of each of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip (see figure 10 and paragraph [0049]-[0050]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to the first and second underfill portions respectively covering at least a portion of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip; and an encapsulant covering at least a portion of each of the plurality of first semiconductor chips and at least a portion of the second semiconductor chip in the device of SEO in order to protect the semiconductor chips. [Re claim 16] SEO discloses the semiconductor package wherein widths of the plurality of adhesive films (160) in the horizontal direction are same as widths of the plurality of first semiconductor chips in the horizontal direction (see figure 8A). [Re claim 17] SEO discloses the semiconductor package wherein each of the plurality of adhesive films have a same width in the horizontal direction (see figure 8A). [Re claim 18] JUNG discloses the semiconductor package wherein side surfaces of the plurality of adhesive films (460) are in contact with the encapsulant (500) (see figure 6). [Re claim 19] SEO discloses the semiconductor package wherein the plurality of adhesive films (160) are apart from each other in a vertical direction (see figure 8A). [Re claim 20] SEO discloses the semiconductor package wherein side surfaces of the conductive bumps (155) are in contact with the plurality of adhesive films (160) (see figure 8A) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 3 and 8-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYOUNG LEE/Primary Examiner, Art Unit 2817 Application/Control Number: 18/678,191 Page 2 Art Unit: 2817 Application/Control Number: 18/678,191 Page 3 Art Unit: 2817 Application/Control Number: 18/678,191 Page 4 Art Unit: 2817
Prosecution Insights