DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claims filed on 01/26/2026. Claims 1 and 8 have been amended. Claims 1-14 remain pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No.CN202311121986.3, filed on 09/01/2023.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/26/2026 has been entered.
Response to Amendments and Arguments
Applicant's arguments filed on 01/26/2026 have been fully considered, with the Examiner’s response set forth below.
(1)Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(2) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US2023/0367491), hereinafter Zhao in view of Yokoi (US 2024/0020010), hereinafter Yokoi, further in view of Kasichainula (US2021/0328944), hereinafter Kasichainula.
Regarding claims 1 and 8, taking claim 1 as exemplary, Zhao teaches a solid-state storage device (Zhao, [0015], a memory system 110 may be or include … a solid-state drive (SSD); [0028]; Fig.1, memory device 130) configured to be electrically connected to a host (Zhao, Fig.1, host 105), the solid-state storage device comprising:
a controller (Zhao, [0024], the memory system 110 may additionally or alternatively rely upon …or one or more local controllers 135, which may be internal to memory devices 130; Fig.1, local controller 135);
a cache memory, electrically connected to the controller (Zhao, [0023], the local memory 120 may serve as a cache for the memory system controller 115; [0024], the memory system 110 may additionally or alternatively rely upon an external controller … or one or more local controllers 135, which may be internal to memory devices 130, respectively, to perform the functions ascribed herein to the memory system controller 115; Note – since local controller 135 serves as a replacement for memory system controller 115, the local memory 120 of the memory system controller 115 would be incorporated into the local controller 135), wherein the cache memory comprises a first region and a second region;
a volatile memory, electrically connected to the controller (Zhao, 0024]; [0040], a storage controller 230 may implement aspects of a local controller 135; Fig.2, buffer queue 265); and
a non-volatile memory (Zhao, [0028], a memory device 130 may be or include a NAND device), electrically connected to the controller (Zhao, Fig.1);
wherein the controller is configured to fetch an access command from the host, and to store the fetched access command in the first region (Zhao, [0047], If a host system 205 transmits access commands to the memory system 210, the commands may be received by the interface 220 … Upon receipt of each access command, the interface 220 may communicate the command to the memory system controller 215, e.g., via the bus 235. In some cases, each command may be added to a command queue 260);
wherein the controller is configured to back up the fetched access command stored in the first region to the volatile memory (Zhao, [0052], the commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215 ); and
wherein the controller is configured to store the fetched access command backed up in the volatile memory in the second region as a ready-to-execute command, and to execute the ready-to-execute command stored in the second region (Zhao, [0054]; [0055], the memory system controller 215 may push (e.g., via the bus 235) write commands from the buffer queue 265 to the storage queue 270 for processing; [0058]; [0059]).
Zhao teaches a buffer queue (i.e. 265) in a storage controller, nevertheless, Zhao does not explicitly teach the buffer queue is a volatile memory, as claimed. Zhao teaches a cache memory (i.e. 120) located in a storage controller, nevertheless, Zhao does not explicitly teach wherein the cache memory comprises a first region and a second region, as claimed.
However, Zhao in view of Yokoi teaches wherein the controller is configured to back up the fetched access command stored in the first region to the volatile memory (Yokoi, Fig.9B, see write commands are stored in buffer area which is a portion of DRAM 102D; Zhao, [0052], the commands in the command queue 260 may be moved to the buffer queue 265 by the memory system controller 215).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhao to incorporate teachings of Yokoi to store I/O commands in a volatile memory queue. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhao with Yokoi because it improves efficiency and performance of the storage system disclosed in Zhao by allowing I/O access with reduced latency.
The combination of Zhao does not explicitly teach wherein the cache memory comprises a first region and a second region, as claimed.
However, the combination of Zhao in view of Kasichainula teaches wherein the cache memory comprises a first region and a second region (Yokoi, [0068], The storage controller 102 further incorporates a network interface 104 as an interface apparatus between the storage controller 102 and the server system 100; [0069]; Fig. 1; Kasichainula, [0007], network interface circuitry (NIC); [0081], the NIC 604 includes ... example data cache 610; [0084], memory in the example data cache 610 is allocated to queues of the data cache 610 … the data cache 610 includes eight queues of which an example first queue 634, an example second queue 636; [0055], transmit queues and .. receive queues to accommodate the different traffic class; Zhao, [0058], the memory system controller 215 may move the command processed by the storage queue 270 back to the command queue 260 );
wherein the controller is configured to fetch an access command from the host, and to store the fetched access command in the first region (Zhao, [0047]; [0045], queues, if used, may be positioned anywhere within the memory system 210);
wherein the controller is configured to store the fetched access command backed up in the volatile memory in the second region (Zhao, [0055]; [0045], queues, if used, may be positioned anywhere within the memory system 210).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhao to incorporate teachings of Kasichainula to partition a cache memory into different regions and each of the regions is allocated to a command queue, such as command queues 260 and 270 (in Zhao). A person of ordinary skill in the art would have been motivated to combine the teachings of Zhao with Kasichainula because it improves efficiency and performance of the storage system disclosed in the combination of by Zhao by allowing I/O access with reduced latency.
Claim 8 has similar limitations as claim 1 and is rejected for the similar reasons.
Regarding claims 2 and 9, taking claim 2 as exemplary, the combination of Zhao teaches all the features with respect to claim 1 as outlined above. The combination of Zhao further teaches the solid-state storage device of Claim 1, wherein the first region is a command-fetching region (Zhao, [0047], If a host system 205 transmits access commands to the memory system 210, the commands may be received by the interface 220 … Upon receipt of each access command, the interface 220 may communicate the command to the memory system controller 215, e.g., via the bus 235. In some cases, each command may be added to a command queue 260), and the second region is a command-execution region (Zhao, [0054]; [0055], the memory system controller 215 may push (e.g., via the bus 235) write commands from the buffer queue 265 to the storage queue 270 for processing; [0058]; [0059]; Kasichainula, [0084]).
Claim 9 has similar limitations as claim 2 and is rejected for the similar reasons.
Claim(s) 3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhao, Yokoi, and Kasichainula as applied to claims 1 and 8 respectively above, and further in view of Green et al. (US 2004/0205225), hereinafter Green.
Regarding claims 3 and 10, taking claim 3 as exemplary, the combination of Singh teaches all the features with respect to claim 1 as outlined above. The combination of Zhao does not explicitly teach the solid-state storage device of Claim 1, wherein: the first region comprises a plurality of first entries, and each of the plurality of first entries corresponds to a first mask bit; and the second region comprises a plurality of second entries, and each of the plurality of second entries corresponds to a second mask bit, as claimed.
However, the combination of Zhao in view of Green teaches the solid-state storage device of Claim 1, wherein: the first region comprises a plurality of first entries, and each of the plurality of first entries corresponds to a first mask bit; and the second region comprises a plurality of second entries, and each of the plurality of second entries corresponds to a second mask bit (Green, [0030], once addresses 2 to 5 of the buffer 20 have all been updated the data contained therein is transferred from the first buffer 20 the second buffer 22, again occupying addresses 2 to 5. The update bits for addresses 2 to 5 in the first buffer 20 are reset to zero and the update bits 2 to 5 in the second buffer 22 are set to 1; [0039], [0040]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhao to incorporate teachings of Green to set a binary flag to a first value in a first buffer and set a binary flag to a second value in a second buffer when data is transferred from a first buffer to a second buffer. Binary flags in a buffer can be set/reset together. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhao with Green because it improves efficiency of the storage system disclosed in the combination of Zhao by providing status of each entry in a buffer using a binary flag.
Claim 10 has similar limitations as claim 3 and is rejected for the similar reasons.
Claim(s) 7 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhao, Yokoi, and Kasichainula as applied to claims 1 and 8 respectively above, and further in view of Akkawi et al. (US11,782,832), hereinafter Akkawi.
Regarding claims 7 and 14, taking claim 7 as exemplary, the combination of Zhao teaches all the features with respect to claim 1 as outlined above. The combination of Zhao does not explicitly teach the solid-state storage device of Claim 1, wherein the cache memory further comprises a third region for storing command completion information of the access command that has been executed in the second region, as claimed.
However, the combination of Zhao in view of Akkawi teaches the solid-state storage device of Claim 1, wherein the cache memory further comprises a third region for storing command completion information of the access command that has been executed in the second region (Zhao, [0054]; Akkawi, col.5, lines 39-57, a command queue 238 and a completion queue 239 are allocated in I/O device controller memory 216 … completion queue 239 stores the result of the commands executed by I/O device controller 112/162; Kasichainula, [0084], the data cache 610 includes eight queues of which an example first queue 634, an example second queue 636;).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhao to incorporate teachings of Akkawi to allocate a third region from the data cache 610 (in Kasichainula) for a completion queue which stores results of commands executed by a storage device . A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhao with Akkawi because it improves efficiency and performance of the storage system disclosed in the combination of Zhao by storing command completion information in queue with other command queues in a low latency cache memory.
Claim 14 has similar limitations as claim 7 and is rejected for the similar reasons.
Allowable Subject Matter
Claims 4-6 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites “[t]he solid-state storage device of Claim 3, wherein when the solid-state storage device is booted up, the controller initializes a value of the first mask bit corresponding to each first entry to a first value, and initializes a value of the second mask bit corresponding to each second entry to a second value.”.
The above-noted limitation, in combination with the other limitation of the claims, are neither disclosed nor suggested by the prior art of record. Therefore, in the context of claim 1, 3, and 4 as a whole, the prior art does not teach the claimed subject matter. Thus, the subject matter of claim 4 is allowable. Claim 11 is objected for the similar reasons. Claims 5-6 and 12-13 are depending either directly or indirectly from claims 4 and 11 respectively, and they are objected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sapuntzakis (US2025/0068554) teaches a storage controller includes a number of queues for storing commands to be fetched and executed by a storage device.
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/NANCI N WONG/Primary Examiner, Art Unit 2137
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