DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 22, 2026 has been entered.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on May 30, 2024 and December 11, 2024 have been considered by the examiner.
Response to Amendment
The amendment filed June 22, 2026 has been entered. Claims 1-3 and 5-20 remain pending in this application. Claim 4 has been cancelled at applicant’s request. Claims 1-3, 5-7, 9, 11, 14, and 18-20 have been amended. No claims have been added. No new matter has been added.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,236,997 B2. Although the claims at issue are not identical, they are not patentably distinct from each other, as follows:
18/678401
12236997
Notes
A memory device comprising: a memory cell array comprising a first bank and a second bank, wherein the first bank and the second bank comprise a plurality of memory cell rows,
1. A semiconductor memory device comprising: a memory cell array including a plurality of memory cell rows, wherein each of the plurality of memory cell rows comprises a respective plurality of memory cells;
These are equivalent. A 'plurality of rows' in a multi-bank DRAM includes a first and second bank. While Claim 1 of '997 does not specify multiple banks, the specification discloses sixteen banks with per-blank decoders. Simply identifying two is not a patentable distinction.
the memory cell array configured to store count data for a number of accesses to each memory cell row of the plurality of memory cell rows;
store the counted values as count data in count cells associated with respective ones of the plurality of memory cell rows
Same
a row hammer management circuit configured to: perform a read-modify-write (RMW) operation that reads out count data corresponding to a target memory cell row among the plurality of memory cell rows, update the read-out count data, and write the updated read-out count data in the memory cell array;
a row hammer management circuit configured to:… perform an internal read-update-write operation, wherein the internal read-update-write operation comprises reading the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, updating the count data that was read to obtain updated count data, and writing the updated count data in a respective ones of the count cells of the target memory cell row
Same
and an RMW driver configured to generate a plurality of RMW control signals,
992 fails to claim a RMW driver configured to generate a plurality of RMW control signals.
These signals are generated, however. The specification discloses these signals originate with the command decoder 211 ('992, col.10:63-67). Merely renaming the command decoder to RMW driver does not distinguish between the circuits.
wherein the RMW driver is configured to receive a first precharge command corresponding to the first bank, receive a second precharge command corresponding to the second bank at a different time than the first precharge command,
'992 fails to disclose two separate PRE commands at separate times.
Examiner takes official notice (Under MPEP § 2144.03) that under standard JEDEC DDR SDRAM protocols, PRE is a per-bank command. A PRE command is issued with a bank address and closes only the addressed bank. A memory controller may therefore issue PRE signal to Bank0 at one clock edge and Bank1 at the same or later clock edge. That staggered, per-bank PRE scheduling the ordinary way multi-bank DRAM is operated. Such bank interleaving is known in the industry and not an additional inventive step.
generate a first internal active count update signal corresponding to the first bank based on the first precharge command, and generate a second internal active count update signal corresponding to the second bank based on the second precharge command and in parallel with the first internal active count update signal,
Claim 1 states, "in response to a precharge command applied at a second time point after a first command was applied." While it discloses a first PRE, in does not expressly disclose two PREs at separate times.
While '992 does not expressly name the internal active count update (IACU) signal, the ACU_EN signal in '992 serves the same purpose. One copy per bank, triggered in response to the bank's PRE, separate triggers with the per-bank PRE (PREpb, PREab, and so forth: '992, col.23:17-30). Specifically naming the same pulse 'IACU' does not distinguish from the same functionality.
and wherein, for each of the first precharge command and the second precharge command, the memory device is configured to perform a respective precharge operation on a respective target memory cell row after a predetermined time has elapsed from a time point when the first precharge command and the second precharge command are respectively received by the memory device.
2. The semiconductor memory device of claim 1, wherein the row hammer management circuit is configured to activate a precharge signal at a third time point after the second time point, and wherein the control logic circuit is configured to precharge the target memory cell row in response to the precharge signal.
Same delay, expressly labeled tACU in '992 ('992: col.24:40-44)
Independent Claims 14 and 18 similarly rejected on the grounds of nonstatutory double patenting as being unpatentable over claims 15 and 20, respectively, of U.S. Patent No. 12,236,997 B2. Claims 2-3, 5-13, 16-17, and 19-20 objected to as depending from a rejected independent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-9, 11-15, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) in view of EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho).
Regarding Amended Independent Claim 1, Pan discloses a memory device comprising:
a memory cell array (A memory cell array: Pan, ¶[0010]) comprising
a first bank and a second bank (Banks 0-15: Pan, Figure 1),
wherein the first bank and the second bank comprise
a plurality of memory cell rows (A plurality of memory cell word lines: Pan, ¶[0010]),
the memory cell array configured to
store count data for a number of accesses (Counting row access: Pan, ¶[0014])
to each memory cell row of the plurality of memory cell rows (Counting accesses to each word line: Pan, ¶[0014]);
a row hammer management circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3) configured to:
perform a read-modify-write (RMW) (The Count Control Circuit performing a read adjust write operation: Pan, ¶[004]) operation
that reads out count data (The Count Control Circuit reading out the access count data: Pan, ¶[0014])
corresponding to a target memory cell row among the plurality of memory cell rows (The access count data corresponding to a particular word line: Pan, ¶[0014]),
update the read-out count data (Count Control Circuit 328 adjusting the count data: Pan, ¶[0014), and
write the updated read-out count data in the memory cell array (Writing the access count data back to the word line: Pan, ¶[0014]); and
an RMW driver configured to
generate a plurality of RMW control signals (A circuit configured to control row count operations: Pan, Figure 3),
wherein the RMW driver is configured to
receive a first precharge command corresponding to the first bank (Waiting to write the access count back to the wordline until receiving a PreCharge command: Pan, ¶[0079]),
receive a second precharge command corresponding to the second bank at a different time than the first precharge command,
generate a first internal active count update signal corresponding to the first bank based on the first precharge command (Generating a count update signal in response to the first precharge signal: Pan, ¶[0079]), and
generate a second internal active count update signal corresponding to the second bank based on the second precharge command and in parallel with the first internal active count update signal,
wherein, for each of the first precharge command and the second precharge command, the memory device is configured to perform a respective precharge operation on a respective target memory cell row
after a predetermined time has elapsed (A PreCharge delay: Pan, ¶[0079])
from a time point when the first precharge command and the second precharge command are respectively received by the memory device (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]). Pan does not expressly teach a second precharge command directed to a second bank at a time different from the first precharge command, or two internal count-update operations generated from those two commands and overlapping in time. Examiner takes official notice (Under MPEP § 2144.03), however, that under standard JEDEC DDR SDRAM protocols, PRE is a per-bank command. A PRE command is issued with a bank address and closes only the addressed bank. A memory controller may therefore issue PRE signal to Bank0 at one clock edge and Bank1 at the same or later clock edge. That staggered, per-bank PRE scheduling the ordinary way multi-bank DRAM is operated. Such bank interleaving is known in the industry and not an additional inventive step.
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to take the known and ordinary method of bank interleaving and applying it to the already bank-independent circuitry of Pan, with a reasonable expectation of success. Once PRE is recognized as a per-bank command that can arrive at different times to different banks, as required by JEDEC, the same mapping already taught by Pan produces the required staggered effect. If the update window is longer than the interval between the two PRE commands, then the operations will necessarily overlap, that is operate in parallel. This operation avoids the full bank serialization that would otherwise be required, defeating the very multi-bank operation Pan is configured to support. Both inventions are well known in the field of per-bank PRE signals and the combination of known inventions is obvious and not patentable.
Applicant may traverse the official notice. If traversed with adequate specificity, Examiner will supply a JEDEC DDR specification showing PRE as a bank-addressed command that may be issued to different banks at different times.
Pan discloses performing a write operation upon receipt of a precharge command, but omits performing a write operation in response to a precharge command and only implies performing an update (Pan, ¶[0079]). Cho, however, explicitly discloses performing a full read-update-write sequence in response to receiving a precharge instruction (Cho, ¶[0021]). Cho teaches performing this operation in response to a precharge command ensures the precharge operation is included in the command (Cho, ¶[0021]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the precharge signal to trigger an update operation, as in Cho, in conjunction with the update methodology of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 2, Pan discloses the memory device of claim 1, wherein the row hammer management circuit is configured to
perform a first RMW operation with respect to a first target memory cell row (Waiting to write the access count back to the wordline until receiving a PreCharge command: Pan, ¶[0079]) of the first bank based on the first precharge command (Performing row count update operations upon receiving a precharge command: Pan, ¶[0079]), and
perform a second RMW operation with respect to a second target memory cell of the second bank (Waiting to write the access count back to the wordline until receiving a PreCharge command: Pan, ¶[0079]) based on the second precharge command in parallel with the first RMW operation (Performing row count update operations upon receiving a precharge command: Pan, ¶[0079]).
As previously disclosed, Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]), and JEDEC DDR protocols teach the PRE being a per-bank command. By extension, the follow-on RMW operations would be expected to be staggered to the extent of the delay between the two commands. Each bank functions independently and may run individually, simultaneously, or concurrently with greater or lesser degrees of overlap.
Regarding Amended Claim 3, Pan discloses the memory device of claim 2, wherein
the first RMW operation with respect to the first target memory cell row is performed (Updating count values and writing them to the wordline: Pan, ¶[0079])
based on the precharge command (Based on receiving the precharge command: Pan, ¶[0079])
during an active count update time (Performing the count update between receiving the precharge command and the expiration of a delay: Pan, ¶[0079]), and
the first target memory cell row is precharged based on the first precharge command (Precharging the wordline: Pan, ¶[0079])
after the active count update time is elapsed (Providing time between after receiving the precharge command: Pan, ¶[0079])
from the time point where the precharge command is received (Precharging the wordline after a delay: Pan, ¶[0079]).
Regarding Amended Claim 5, Pan discloses the memory device of claim 1, wherein
a section in which the first internal active count update signal corresponding to the first bank is activated (Activating the internal active count update in a bank: Pan, ¶[0014])
overlaps (Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]), and JEDEC DDR protocols teach the PRE being a per-bank command)
a section in which the second internal active count update signal corresponding to the second bank is activated (Activating the internal active count update in a bank: Pan, ¶[0014]).
Regarding Amended Claim 6, Pan discloses the memory device of claim 1, wherein the RMW driver is configured to:
generate a first RMW core signal group that controls an RMW operation of the first bank (Controlling the RMW signal in a bank: Pan, ¶[0014])
based on the first internal active count update signal (Based on a signal: Pan, ¶[0031]), and
generate, in parallel with the first RMW core signal group, a second RMW core signal group (Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]), and JEDEC DDR protocols teach the PRE being a per-bank command)
that controls an RMW operation of the second bank (Controlling the RMW signal in a bank: Pan, ¶[0014])
based on the second internal active count update signal (Based on a signal: Pan, ¶[0031]).
Regarding Amended Claim 7, Pan and Cho disclose the memory device of claim 1, wherein the RMW driver comprises:
an internal active count update signal generator (A count control circuit 328: Pan, Figure 3) configured to
based on each precharge command (In response to a precharge command: Cho, ¶[0021]),
generate a respective internal active count update signal (Generate a Read-Modify-Write operation: Cho, ¶[0021])
with respect to a bank corresponding to the precharge command (The circuitry associated with a particular bank: Cho, Figure 3); and
a plurality of RMW control circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3)
each RMW control circuit configured to generate,
based on an internal active count update signal (Generate a Read-Modify-Write operation: Cho, ¶[0021]) received by the RMW control circuit,
a respective RMW core signal group (Generating a signal to perform a RMW operation: Cho, ¶[0021])
that controls an RMW operation of a bank corresponding to a respective precharge command (Circuitry associated with a particular bank: Pan, ¶[0054]).
Regarding Claim 8, Pan discloses the memory device of claim 7, wherein the internal active count update signal generator is configured to
maintain a level of the internal active count update signal at a high level during the predetermined time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval).
Regarding Amended Claim 9, Pan discloses the memory device of claim 8, wherein the RMW control circuit comprises:
an oscillator configured to generate an oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030])
during the high level of the internal active count update signal (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]); and
a core signal generator configured to generate,
based on a rising edge or a falling edge of the oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]),
the respective RMW core signal group that controls the RMW operation of the bank corresponding to the respective precharge command (Updating the access count in accordance with the precharge signal: Pan, ¶[0031]).
Regarding Amended Claim 11, Pan discloses the memory device of claim 1, comprising
a control logic circuit configured to generate,
based on each precharge command (In response to a precharge signal: Pan, ¶[0055]),
a respective internal precharge signal that precharges the respective target memory cell row (The given bank being precharged in response to a precharge signal: Pan, ¶[0055])
after the predetermined time has elapsed from the time point where the respective precharge command is received (Precharging the designated lines after a predetermined delay following the receipt of a precharge command: Pan, ¶[0079]).
Regarding Claim 12, Pan discloses the memory device of claim 1, wherein the row hammer management circuit is configured
to perform a refresh operation on a memory cell row (Performing a refresh operation on a victim row: Pan, ¶[0012])
adjacent to the target memory cell row (A victim row being one adjacent to a frequently accessed row: Pan, ¶[0064])
based on a value of the updated read-out count data being equal to or greater than a predetermined value (The refresh operation taking place in response to a number of access of a row reaches a predetermined threshold: Pan, ¶[0012]).
Regarding Claim 13, Pan discloses the memory device of claim 1, comprising
an ECC engine configured to perform an error correction operation on the read-out count data (Using ECC to correct errors in the read count: Pan, ¶[0077]).
Regarding Independent Claim 14, Pan discloses a memory device comprising:
a memory cell array (A memory cell array: Pan, ¶[0010]) comprising
a first bank and a second bank (The memory array divided into separate banks of memory: Pan, ¶[0019])
comprising a plurality of memory cell rows (A plurality of memory cell word lines: Pan, ¶[0010]);
a row hammer management circuit (A refresh control circuit 316 and a Count Control Circuit 328: Pan, Figure 3) configured
to perform a first read-modify-write (RMW) operation (The Count Control Circuit performing a read adjust write operation: Pan, ¶[004])
with respect to the first bank (Disclosing circuitry controlling the count operations being repeated for each bank: Pan, ¶[0054]) and
a second RMW operation (The Count Control Circuit performing a read adjust write operation: Pan for a bank, ¶[004]); and
an RMW driver configured to
generate a first RMW core signal group (A circuit configured to control row count operations: Pan, Figure 3) and
a second RMW core signal group (A circuit configured to control row count operations: Pan, Figure 3),
the first RMW core signal group controlling the first RMW operation with respect to the first bank (A circuit configured to control row count operations: Pan, Figure 3) and
the second RMW core signal group controlling the second RMW operation with respect to the second bank (A circuit configured to control row count operations: Pan, Figure 3), wherein
the RMW driver is configured to generate the first RMW core signal group based on a first precharge command received at a first time with respect to the first bank (Waiting to write the access count back to the wordline until receiving a PreCharge command: Pan, ¶[0079]) and
generate the second RMW core signal group based on a second precharge command received at a second time with respect to the second bank (Waiting to write the access count back to the wordline until receiving a PreCharge command: Pan, ¶[0079]),
wherein the first time is different from the second time,
wherein a first precharge operation
corresponding to the first precharge command (In response to a precharge command: Pan, ¶[0079])
is performed after a time delay (A PreCharge delay: Pan, ¶[0079])
by an active count update time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]) from a time point when the first precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]), and
wherein a second precharge operation
corresponding to the second precharge command (In response to a precharge command: Pan, ¶[0079])
is performed after a time delay (A PreCharge delay: Pan, ¶[0079])
by the active count update time (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]) from a time point when the second precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]). Pan does not expressly teach a second precharge command directed to a second bank at a time different from the first precharge command, or two internal count-update operations generated from those two commands and overlapping in time. Examiner takes official notice (Under MPEP § 2144.03), however, that under standard JEDEC DDR SDRAM protocols, PRE is a per-bank command. A PRE command is issued with a bank address and closes only the addressed bank. A memory controller may therefore issue PRE signal to Bank0 at one clock edge and Bank1 at the same or later clock edge. That staggered, per-bank PRE scheduling the ordinary way multi-bank DRAM is operated. Such bank interleaving is known in the industry and not an additional inventive step.
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to take the known and ordinary method of bank interleaving and applying it to the already bank-independent circuitry of Pan, with a reasonable expectation of success. Once PRE is recognized as a per-bank command that can arrive at different times to different banks, as required by JEDEC, the same mapping already taught by Pan produces the required staggered effect. If the update window is longer than the interval between the two PRE commands, then the operations will necessarily overlap, that is operate in parallel. This operation avoids the full bank serialization that would otherwise be required, defeating the very multi-bank operation Pan is configured to support. Both inventions are well known in the field of per-bank PRE signals and the combination of known inventions is obvious and not patentable.
Applicant may traverse the official notice. If traversed with adequate specificity, Examiner will supply a JEDEC DDR specification showing PRE as a bank-addressed command that may be issued to different banks at different times.
Pan discloses performing a write operation upon receipt of a precharge command, but omits performing a write operation in response to a precharge command and only implies performing an update (Pan, ¶[0079]). Cho, however, explicitly discloses performing a full read-update-write sequence in response to receiving a precharge instruction (Cho, ¶[0021]). Cho teaches performing this operation in response to a precharge command ensures the precharge operation is included in the command (Cho, ¶[0021]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the precharge signal to trigger an update operation, as in Cho, in conjunction with the update methodology of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 15, Pan discloses the memory device of claim 14, comprising
a control logic circuit configured to
generate a first internal precharge signal and a second internal precharge signal (Precharging the wordline in response to a signal: Pan, ¶[0079])
based on the first precharge command and the second precharge command, respectively (Updating count values and writing them to a wordline in response to receiving a precharge command: Pan, ¶[0079]),
wherein the first internal precharge signal is generated after the time delay (A PreCharge delay: Pan, ¶[0079]) by the active count update time from the time point where the first precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]), and
the second internal precharge signal is generated after the time delay (A PreCharge delay: Pan, ¶[0079]) by the active count update time from the time point where the second precharge command is received (The delay implemented between receiving the precharge command and performing the precharge operation: Pan, ¶[0079]).
Regarding Independent Claim 18, Pan discloses a method of operating a memory device, comprising:
receiving a first precharge command corresponding to a first target memory cell row of a first bank (Receiving a precharge command: Pan, ¶[0079]);
receiving a second precharge command at a different time from the first precharge command, wherein the second precharge command corresponds to a second target memory cell row of a second bank;
generating, based on the first precharge command,
a first internal active count update signal (Performing row count update operations upon receiving a precharge command: Pan, ¶[0079])
corresponding to the first target memory cell row (Corresponding to the row: Pan, ¶[0079]);
generating, based on the second precharge command and in parallel with generating the first precharge command, a second internal active count update signal corresponding to the second target memory cell row;
generating, based on the first internal active count update signal,
a first plurality of control signals that update count data with respect to the first target memory cell row (Updating the count data with respect to the row: Pan, ¶[0079]);
generating, based on the second internal active count update signal, a second plurality of control signals in parallel with generating the first plurality of control signals, wherein the second plurality of control signals update count data with respect to the second target memory cell rows;
performing, based on the first precharge command (In response to the precharge command: Pan, ¶[0079]),
a first precharge operation on the first target memory cell row after an active count update time is elapsed (Performing the precharge operation after the expiration of a delay: Pan, ¶[0079])
from a time point when the first precharge command is received (Performing the precharge operation after a delay starting from when the precharge command is received: Pan, ¶[0079]); and
performing, based on the second precharge command, a second precharge operation on the second target memory cell row after an active count update time is elapsed from a time point when the second precharge command is received.
Pan discloses each bank of memory including a duplicate of the key circuitry, including but not limited to row decoder, DRAM interface, memory array, refresh control circuit, and count control circuit (Pan, ¶[0054]). Pan does not expressly teach a second precharge command directed to a second bank at a time different from the first precharge command, or two internal count-update operations generated from those two commands and overlapping in time. Examiner takes official notice (Under MPEP § 2144.03), however, that under standard JEDEC DDR SDRAM protocols, PRE is a per-bank command. A PRE command is issued with a bank address and closes only the addressed bank. A memory controller may therefore issue PRE signal to Bank0 at one clock edge and Bank1 at the same or later clock edge. That staggered, per-bank PRE scheduling the ordinary way multi-bank DRAM is operated. Such bank interleaving is known in the industry and not an additional inventive step.
Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to take the known and ordinary method of bank interleaving and applying it to the already bank-independent circuitry of Pan, with a reasonable expectation of success. Once PRE is recognized as a per-bank command that can arrive at different times to different banks, as required by JEDEC, the same mapping already taught by Pan produces the required staggered effect. If the update window is longer than the interval between the two PRE commands, then the operations will necessarily overlap, that is operate in parallel. This operation avoids the full bank serialization that would otherwise be required, defeating the very multi-bank operation Pan is configured to support. Both inventions are well known in the field of per-bank PRE signals and the combination of known inventions is obvious and not patentable.
Applicant may traverse the official notice. If traversed with adequate specificity, Examiner will supply a JEDEC DDR specification showing PRE as a bank-addressed command that may be issued to different banks at different times.
Pan discloses performing a write operation upon receipt of a precharge command, but omits performing a write operation in response to a precharge command and only implies performing an update (Pan, ¶[0079]). Cho, however, explicitly discloses performing a full read-update-write sequence in response to receiving a precharge instruction (Cho, ¶[0021]). Cho teaches performing this operation in response to a precharge command ensures the precharge operation is included in the command (Cho, ¶[0021]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the precharge signal to trigger an update operation, as in Cho, in conjunction with the update methodology of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 19, Pan discloses the method of claim 18, comprising
performing a first read-modify-write (RMW) operation (Reading, updating, and writing a row access count: Pan, ¶[0014]),
wherein the first RMW operation
reads out count data corresponding to the first target memory cell row during the active count update time (Reading out the number of row accesses performed within a set period of time: Pan, ¶[0014]),
updates the read-out count data (Updating the read count data: Pan, ¶[0014]), and
writes the updated read-out count data in a memory cell array (Writing back the updated count data: Pan, ¶[0014]).
Regarding Amended Claim 20, Pan discloses the method of claim 18, comprising
performing a first refresh operation on a memory cell row (Performing a refresh operation on a victim row: Pan, ¶[0012])
adjacent to the first target memory cell row (A victim row being one adjacent to a frequently accessed row: Pan, ¶[0064])
based on a value of the count data with respect to the first target memory cell row being equal to or greater than a predetermined value (The refresh operation taking place in response to a number of access of a row reaches a predetermined threshold: Pan, ¶[0012]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) and EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho) in view of US 9,362,006 B2 to Yohan U. Frans, et al. (hereafter Frans).
Regarding Claim 10, Pan discloses the memory device of claim 9, but fails to disclose the further limitations of Claim 10. Frans, however, discloses a memory device, wherein
the oscillation signal has a frequency that changes (A changing oscillation circuit: Frans, col.1:64-66)
as an operation frequency of the memory device changes (The clock signal changing in response to broader device circumstances: Frans, col.2:4-10).
Frans teaches tracking clock signal frequency variations can help account for timing drift due to external factors such as due to temperature or device state (Frans, col.1:21-37). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the clock variation tracking of Frans with the timing circuit of Pan, with a reasonable expectation of success. Both inventions are well known in the field of time interval tracking in memory devices and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0165347 A1 to Dong Pan (hereafter Pan) and EP 4,123,650 A1 to Sungyong Cho, et al. (hereafter Cho) in view of US 2014/0059287 A1 to Kuljit Bains, et al. (hereafter Bains).
Regarding Claim 16, Pan and Cho disclose the memory device of claim 15, wherein
the RMW driver comprises an internal active count update signal generator (A count control circuit 328: Pan, Figure 3) configured to:
generate
a first internal active count update signal corresponding to the first bank (Generate a Read-Modify-Write operation: Cho, ¶[0021]) and
a second internal active count update signal corresponding to the second bank (Generate a Read-Modify-Write operation: Cho, ¶[0021]).
Pan fails to disclose the further limitations of Claim 16. Bains, however, discloses a memory device as in Claim 15, configured to:
transition a level of the first internal active count update signal from a low level to a high level based on the first precharge command (Transitioning from a low to high signal based on a command: Bains, Figure 5),
transition the level of the first internal active count update signal from the high level to the low level based on the first internal precharge signal (Transitioning from a low to high signal based on a command: Bains, Figure 5),
transition a level of the second internal active count update signal from the low level to the high level (Transitioning from a high level to a low level: Bains, Figure 5) based on the second precharge command (In response to a second command: Bains, ¶[0058]), and
transition the level of the second internal active count update signal from the high level to the low level (Transitioning from a high level to a low level: Bains, Figure 5) based on the second internal precharge signal (In response to a second command: Bains, ¶[0058]).
Bains teaching switching between data states in response to command signals allows a single bit to track multiple command signals (Bains, ¶[0061]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the combine signal method of Bains to implement the precharge signals of Pan, with a reasonable expectation of success. Both inventions are well known in the field of row hammer mitigation methods and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Pan discloses the memory device of claim 16, wherein
the RMW driver comprises an RMW control circuit configured to:
generate the first RMW core signal group corresponding to the first bank based on the first internal active count update signal (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval), and
generate the second RMW core signal group corresponding to the second bank based on the second internal active count update signal (Disclosing incrementing the access count only for operations performed during a certain interval of time: Pan, ¶[0014]; Tracking the lapse of time via some sort of signal is inherent in tracking a time interval), and
wherein the RMW control circuit comprises:
an oscillator configured to:
generate a first oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030]) during a time in which the first internal active count update signal is maintained at the high level (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]), and
generate a second oscillation signal (Count Control Circuit 128 including a timer in the form of a clock: Pan, ¶[0030]) during a time in which the second internal active count update signal is maintained at the high level (The row count window tracked by clock cycles: Pan, ¶¶[0014] and [0030]); and
a core signal generator configured to:
generate the first RMW core signal group based on a rising edge or a falling edge of the first oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]), and
generate the second RMW core signal group based on a rising edge or a falling edge of the second oscillation signal (The Count Control Circuit updating the count based on the clock signal: Pan, ¶[0030]).
Response to Arguments
Applicant’s arguments filed June 22, 2026 have been fully considered by they are not persuasive.
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JEDEC Standard for DDR4 SDRAM, JESD79-4C, Revised January 2020 by JEDEC Solid State Technology Association: Teaching staggered per-bank PRE scheduling is an ordinary way multi-bank DRAM is operated.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
