DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-16 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6, 9-10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH et al. USPGPUB 2016/0306592 (hereinafter “OH”).
Regarding claim 1, OH teaches a solid-state storage device ([Abstract] “A storage device is provided which includes a nonvolatile memory”), comprising:
a non-volatile memory ([Abstract] “A storage device is provided which includes a nonvolatile memory”);
a temperature sensor ([Abstract “A storage device is provided which includes a nonvolatile memory and a temperature sensor”), configured to periodically detect a current temperature of the non-volatile memory ([Abstract] “ The temperature sensor is configured to detect a temperature of the storage device”, [Abstract] “The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period”, and Paragraph [0041]); and
a controller ([Abstract] “The storage device includes a memory controller”), electrically connected to the non-volatile memory and the temperature sensor, and configured to periodically obtain the current temperature from the temperature sensor ([Abstract] “A storage device is provided which includes a nonvolatile memory and a temperature sensor”, [Abstract] “The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period”, and Paragraph [0041]);
wherein the controller is configured to activate a dynamic temperature control mechanism of the solid-state storage device, and the dynamic temperature control mechanism comprises a temperature control state table having a plurality of temperature control states and their corresponding state values (Paragraph [0038] “Based on the temperature information, the memory controller 120 or the temperature manager 128 may signal the storage device 100 or the memory controller 120 to operate in one of a first mode M1, a second mode M2, and a third mode M3. The first, second and third modes M1, M2 and M3 will be described in more detail below with reference to FIG. 2”, and Paragraph [0008],Paragraphs [0039-0040], and [FIGS. 3-5], wherein examiner interpreted memory controller signaling storage device to operate in one of the modes as the controller configured to activate a dynamic temperature control mechanism of the solid-state storage device, and wherein examiner interpreted the various temperature information corresponding to different operation modes as the temperature control state table having a plurality of temperature control states and their corresponding state values);
wherein the controller is further configured to calculate a temperature difference value between the current temperature and a previous temperature of the non-volatile memory, and accumulate the temperature difference value to obtain a temperature accumulation value (Paragraph [0064] “Referring to FIGS. 1 and 6, the memory controller 120 may calculate a temperature difference ΔTEM (S410) between the currently detected temperature TEM and the previously detected temperature TEM_P”, Paragraph [0065] “The memory controller 120 may store a variation in the operating speed or the fine detection period P_FINE according to a range of temperature differences ΔTEM. The variation in the operating speed or the fine detection period P_FINE according to a range of temperature differences ΔTEM may be stored in the form of table. Based on the stored table, the memory controller 120 may calculate the variation in the operating speed or fine period P_FINE”, Paragraph [0078] “The memory controller 120 may determine a variation in the operating speed or the fine detection period P_FINE based on the table of the temperature differences ΔTEM described herein”, wherein examiner interpreted calculating temperature difference value between current temperature and previous temperature of non-volatile memory as calculating temperature difference value between current temperature and a previous temperature of non-volatile memory, and wherein examiner interpreted storing temperature differences in the form of table as accumulating temperature difference value to obtaining a temperature accumulation value); and
wherein the controller is further configured to determine a current temperature control state from the temperature control state table according to the temperature accumulation value (Paragraph [0064] “If a temperature difference ΔTEM is detected between the currently detected temperature TEM and the previously detected temperature TEM_P (S420), the memory controller 1200 may calculate a variation in an operating speed or the fine detection period P_FINE, based on the temperature difference ΔTEM (S430)”, Paragraphs [0065-0066], Paragraph [0067] “The memory controller 120 may apply the decided variation (S440). For example, the memory controller 120 may adjust the operating speed or the fine detection period P_FINE based on the decided variation”, wherein examiner interpreted memory controller adjusting operating speed or fine detection period based on the decided variation, wherein the variation is calculated based on temperature differences as controller further configured to determine a current temperature control state from the temperature control state table according to the temperature accumulation value).
Regarding claim 2, OH teaches wherein when the controller determines that the current temperature is higher than a first temperature threshold, the controller is configured to activate the dynamic temperature control mechanism of the solid-state storage device (Paragraph [0041] “the memory controller 120 may detect the temperature TEM by obtaining temperature information from the temperature sensor 140. In each detection period, if the detected temperature TEM is higher than or equal to a first temperature TC1 and lower than a second temperature TC2 (S120), the memory controller 120 may enter the fine control mode M2 (S125). In each period, if the detected temperature TEM is higher than or equal to the second temperature TC2 (S130), the memory controller 120 may enter the low heat mode M3 (S135). In each detection period, if the detected temperature TEM is lower than the first temperature TC1, the memory controller 120 may maintain the normal mode M1 (S140)”, wherein examiner interpreted temperature being within first and second temperature to control which mode of operation to enter as when the controller determines that the current temperature is higher than a first temperature threshold, the controller is configured to activate the dynamic temperature control mechanism of the solid-state storage device, wherein examiner interpreted detected temperature being greater than TC2 as current temperature is higher than a first temperature threshold).
Regarding claim 6, OH teaches wherein when the controller activates the dynamic temperature control mechanism, the controller sets an initial temperature control state from the temperature control states within the temperature control state table as the current temperature control state (Paragraph [0040] “The memory controller 120 may operate in the first mode M1 or may operate in the second mode M2 or the third mode M3 based on a temperature of the storage device 100. The memory controller 120 may switch between the first, second and third modes M1, M2 and M3 based on a temperature of the storage device 100. An exemplary embodiment of the present inventive concept in which the memory controller 120 operates in the first mode M1 is illustrated in FIG. 3”, and Paragraph [0041], wherein examiner interpreted controller operating in different operation modes based on temperature as controller activating the dynamic temperature control mechanism, wherein examiner interpreted different temperature ranges as setting initial temperature control state from the temperature control states within the temperature control state table as the current temperature control state).
Regarding claim 9, OH teaches a dynamic temperature control method, for use in a solid-state storage device, wherein the solid-state storage device comprises a controller, a temperature sensor, and a non-volatile memory (Paragraph [0020] “an operating method of a storage device which includes a nonvolatile memory, a temperature sensor and a memory controller connected to the nonvolatile memory. The operating method includes detecting a temperature using a temperature sensor according to a first period… The operating method includes adjusting an operating speed of the memory controller based on the second temperature”), the method comprising:
utilizing the temperature sensor to periodically detect a current temperature of the non-volatile memory ([Abstract “A storage device is provided which includes a nonvolatile memory and a temperature sensor”, [Abstract] “ The temperature sensor is configured to detect a temperature of the storage device”, [Abstract] “The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period”, and Paragraph [0041]);
utilizing the controller to periodically obtain the current temperature from the temperature sensor ([Abstract] “The storage device includes a memory controller”, [Abstract] “A storage device is provided which includes a nonvolatile memory and a temperature sensor”, [Abstract] “The memory controller is configured to obtain the temperature information from the temperature sensor according to a first period in a first mode. The temperature sensor is configured to obtain the temperature information from the temperature sensor according to a second period in a second mode. The second period is shorter than the first period”, and Paragraph [0041]);
utilizing the controller to activate a dynamic temperature control mechanism of the solid-state storage device, wherein the dynamic temperature control mechanism comprises a temperature control state table having a plurality of temperature control states and their corresponding state values (Paragraph [0038] “Based on the temperature information, the memory controller 120 or the temperature manager 128 may signal the storage device 100 or the memory controller 120 to operate in one of a first mode M1, a second mode M2, and a third mode M3. The first, second and third modes M1, M2 and M3 will be described in more detail below with reference to FIG. 2”, and Paragraph [0008],Paragraphs [0039-0040], and [FIGS. 3-5], wherein examiner interpreted memory controller signaling storage device to operate in one of the modes as the controller configured to activate a dynamic temperature control mechanism of the solid-state storage device, and wherein examiner interpreted the various temperature information corresponding to different operation modes as the temperature control state table having a plurality of temperature control states and their corresponding state values);
utilizing the controller to calculate a temperature difference value between the current temperature and a previous temperature of the non-volatile memory, and to accumulate the temperature difference value to obtain a temperature accumulation value (Paragraph [0064] “Referring to FIGS. 1 and 6, the memory controller 120 may calculate a temperature difference ΔTEM (S410) between the currently detected temperature TEM and the previously detected temperature TEM_P”, Paragraph [0065] “The memory controller 120 may store a variation in the operating speed or the fine detection period P_FINE according to a range of temperature differences ΔTEM. The variation in the operating speed or the fine detection period P_FINE according to a range of temperature differences ΔTEM may be stored in the form of table. Based on the stored table, the memory controller 120 may calculate the variation in the operating speed or fine period P_FINE”, Paragraph [0078] “The memory controller 120 may determine a variation in the operating speed or the fine detection period P_FINE based on the table of the temperature differences ΔTEM described herein”, wherein examiner interpreted calculating temperature difference value between current temperature and previous temperature of non-volatile memory as calculating temperature difference value between current temperature and a previous temperature of non-volatile memory, and wherein examiner interpreted storing temperature differences in the form of table as accumulating temperature difference value to obtaining a temperature accumulation value); and
utilizing the controller to determine a current temperature control state from the temperature control state table according to the temperature accumulation value (Paragraph [0064] “If a temperature difference ΔTEM is detected between the currently detected temperature TEM and the previously detected temperature TEM_P (S420), the memory controller 1200 may calculate a variation in an operating speed or the fine detection period P_FINE, based on the temperature difference ΔTEM (S430)”, Paragraphs [0065-0066], Paragraph [0067] “The memory controller 120 may apply the decided variation (S440). For example, the memory controller 120 may adjust the operating speed or the fine detection period P_FINE based on the decided variation”, wherein examiner interpreted memory controller adjusting operating speed or fine detection period based on the decided variation, wherein the variation is calculated based on temperature differences as controller further configured to determine a current temperature control state from the temperature control state table according to the temperature accumulation value).
Regarding claim 10, OH teaches further comprising: wherein when the controller determines that the current temperature is higher than a first temperature threshold, utilizing the controller to activate the dynamic temperature control mechanism of the solid-state storage device (Paragraph [0041] “the memory controller 120 may detect the temperature TEM by obtaining temperature information from the temperature sensor 140. In each detection period, if the detected temperature TEM is higher than or equal to a first temperature TC1 and lower than a second temperature TC2 (S120), the memory controller 120 may enter the fine control mode M2 (S125). In each period, if the detected temperature TEM is higher than or equal to the second temperature TC2 (S130), the memory controller 120 may enter the low heat mode M3 (S135). In each detection period, if the detected temperature TEM is lower than the first temperature TC1, the memory controller 120 may maintain the normal mode M1 (S140)”, wherein examiner interpreted temperature being within first and second temperature to control which mode of operation to enter as when the controller determines that the current temperature is higher than a first temperature threshold, the controller is configured to activate the dynamic temperature control mechanism of the solid-state storage device, wherein examiner interpreted detected temperature being greater than TC2 as current temperature is higher than a first temperature threshold).
Regarding claim 14, OH teaches further comprising: when the controller activates the dynamic temperature control mechanism, utilizing the controller to set an initial temperature control state from the temperature control states within the temperature control state table as the current temperature control state (Paragraph [0040] “The memory controller 120 may operate in the first mode M1 or may operate in the second mode M2 or the third mode M3 based on a temperature of the storage device 100. The memory controller 120 may switch between the first, second and third modes M1, M2 and M3 based on a temperature of the storage device 100. An exemplary embodiment of the present inventive concept in which the memory controller 120 operates in the first mode M1 is illustrated in FIG. 3”, and Paragraph [0041], wherein examiner interpreted controller operating in different operation modes based on temperature as controller activating the dynamic temperature control mechanism, wherein examiner interpreted different temperature ranges as setting initial temperature control state from the temperature control states within the temperature control state table as the current temperature control state).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-5, and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. USPGPUB 2016/0306592 (hereinafter “OH”), in view of CHANG USPGPUB 2024/0428867 (hereinafter “CHANG”).
Regarding claim 3, OH teaches all of the features with respect to claim 1 as outlined above.
OH does not explicitly teach further comprising: a clock generator, configured to provide a first clock signal to the controller, and provide a second clock signal to the non-volatile memory, wherein a frequency of the first clock signal is higher than that of the second clock signal, and a number of steps of the first clock signal and the second clock signal is determined by the current temperature control state.
However, CHANG teaches further comprising: a clock generator, configured to provide a first clock signal to the controller, and provide a second clock signal to the non-volatile memory ([Abstract] “The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory”), wherein a frequency of the first clock signal is higher than that of the second clock signal (Paragraph [0022] “The first clock generator 106 and the second clock generator 108 respectively generate a first clock Clk1 and a second clock Clk2. The multiplexer 110 is controlled by a selection signal Sel from the controller 104, to output the first clock Clk1 or the second clock Clk2 as the clock signal Clk for operating the flash memory 102. The frequency of the second clock Clk2 is lower than that of the first clock Clk1. For example, the first clock Clk1 may be as high as 1000 MHz or more, while the second clock Clk2 may be only tens of MHz”), and a number of steps of the first clock signal and the second clock signal is determined by the current temperature control state (Paragraph [0026] “In the figure, the numerical values DT1, DT2, and DT3 each show a temperature difference criteria. The numerical values CD1, CD2, CD3, and CD4 each represent a time proportion, where CD1<CD2<CD3<CD4. When the temperature difference ΔT (which is the sensed temperature Ts minus the first critical temperature TMTU) does not reach DT1, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD1. When the temperature difference ΔT reaches the DT1 but does not reach the DT2, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD2. When the temperature difference ΔT reaches the DT2 but does not reach the DT3, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD3. When the temperature difference ΔT reaches the DT3, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD4. In an example, DT1 is 5, DT2 is 10, DT3 is 15, CD1 is 2, CD2 is 4, CD3 is 6, and CD4 is 8. The illustration shows the adaptive cooling strategy is divided into four levels of control. In the other example, there may be a different number of control levels, other than four”, and Paragraph [0027] “To summarize, in response to the sensed temperature Ts exceeding the first critical temperature TMTU, the controller 104 adjusts a time ratio of enabling the first clock Clk1 and the second clock Clk2 according to the magnitude that the sensed temperature Ts exceeds the first critical temperature TMTU”, and Paragraphs [0031-0032], wherein examiner interpreted enabling and disabling clock generator with a time ratio depending on the temperature difference as the number of steps of the first clock signal and a second clock signal determined by the current temperature control state, wherein examiner interpreted time ratios as the number of steps of first clock signal and the second clock signal).
OH, and CHANG are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to storage devices.
Therefore, before the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above solid-state storage device, as taught by OH, and incorporating a clock generator, as taught by CHANG.
One of ordinary skill in the art would have been motivated to improve efficiently controlling non-volatile memory as suggested by CHANG (see Paragraph [0005-0007]).
Regarding claim 4, OH, and CHANG teaches all of the features with respect to claim 3 as outlined above.
CHANG further teaches wherein the number of steps of the first clock signal and the second clock signal represent frequency division ratios of the first clock signal and the second clock signal (Paragraph [0027] “To summarize, in response to the sensed temperature Ts exceeding the first critical temperature TMTU, the controller 104 adjusts a time ratio of enabling the first clock Clk1 and the second clock Clk2 according to the magnitude that the sensed temperature Ts exceeds the first critical temperature TMTU”, Paragraph [0022] “The frequency of the second clock Clk2 is lower than that of the first clock Clk1. For example, the first clock Clk1 may be as high as 1000 MHz or more, while the second clock Clk2 may be only tens of MHz”, wherein examiner interpreted time ratio of enabling first and second clock as the number of steps of the first clock signal and the second clock signal representing frequency division ratios of the first clock signal and the second clock signal).
Regarding claim 5, OH, and CHANG teaches all of the features with respect to claim 3 as outlined above.
CHANG further teaches wherein the number of steps of the first clock signal and the second clock signal represent frequency reduction ratios of the first clock signal and the second clock signal (FIG. 3 illustrates temperature modulation control in accordance with an exemplary embodiment. In this example, in addition to the first critical temperature TMTU for initiating the adaptive cooling strategy, a second critical temperature TM_L and a third critical temperature TM_H are introduced, where TM_L<TM_H<TMTU. In response to the sensed temperature Ts exceeding the second critical temperature TM_L but not exceeding the third critical temperature TM_H, the controller 104 performs a first-level underclocking based on the first clock Clk1 generated by the first clock generator 106. Thus, the flash memory 102 is operated at a frequency reduction rate of N1, where N1 is a number less than 100. For example, the (100-N1) % frequency of the first clock Clk1 is used to create a third clock Clk3 to operate the flash memory 102”, and Paragraph [0031] “The controller 104 alternately enables and disables the first clock generator 106 in an adaptive ratio, to alternately switching between the normal transmission state St and the cooling state Sc in the adaptive ratio”, wherein examiner interpreted memory being operated at a frequency reduction rate based on clock signal enabling and disabling clock generator in an adaptive ratio as the number of steps of the first clock signal and the second clock signal represent frequency reduction ratios of the first clock signal and the second clock signal, and Paragraph [0032]).
Regarding claim 11, OH teaches all of the features with respect to claim 9 as outlined above.
OH does not explicitly teach wherein the solid-state storage device further comprises a clock generator, and the method further comprises: utilizing the clock generator to provide a first clock signal to the controller, and to provide a second clock signal to the non-volatile memory, wherein a frequency of the first clock signal is higher than that of the second clock signal, and a number of steps of the first clock signal and the second clock signal is determined by the current temperature control state.
However, CHANG teaches wherein the solid-state storage device further comprises a clock generator, and the method further comprises: utilizing the clock generator to provide a first clock signal to the controller, and to provide a second clock signal to the non-volatile memory ([Abstract] “The data storage device has a first clock generator and a second clock generator, respectively generating a first clock and a second clock, which are selected by a controller to operate a nonvolatile memory”), wherein a frequency of the first clock signal is higher than that of the second clock signal (Paragraph [0022] “The first clock generator 106 and the second clock generator 108 respectively generate a first clock Clk1 and a second clock Clk2. The multiplexer 110 is controlled by a selection signal Sel from the controller 104, to output the first clock Clk1 or the second clock Clk2 as the clock signal Clk for operating the flash memory 102. The frequency of the second clock Clk2 is lower than that of the first clock Clk1. For example, the first clock Clk1 may be as high as 1000 MHz or more, while the second clock Clk2 may be only tens of MHz”), and a number of steps of the first clock signal and the second clock signal is determined by the current temperature control state (Paragraph [0026] “In the figure, the numerical values DT1, DT2, and DT3 each show a temperature difference criteria. The numerical values CD1, CD2, CD3, and CD4 each represent a time proportion, where CD1<CD2<CD3<CD4. When the temperature difference ΔT (which is the sensed temperature Ts minus the first critical temperature TMTU) does not reach DT1, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD1. When the temperature difference ΔT reaches the DT1 but does not reach the DT2, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD2. When the temperature difference ΔT reaches the DT2 but does not reach the DT3, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD3. When the temperature difference ΔT reaches the DT3, the controller 104 alternately enables (St) and disables (Sc) the first clock generator 106 with a time ratio of 1:CD4. In an example, DT1 is 5, DT2 is 10, DT3 is 15, CD1 is 2, CD2 is 4, CD3 is 6, and CD4 is 8. The illustration shows the adaptive cooling strategy is divided into four levels of control. In the other example, there may be a different number of control levels, other than four”, and Paragraph [0027] “To summarize, in response to the sensed temperature Ts exceeding the first critical temperature TMTU, the controller 104 adjusts a time ratio of enabling the first clock Clk1 and the second clock Clk2 according to the magnitude that the sensed temperature Ts exceeds the first critical temperature TMTU”, and Paragraphs [0031-0032], wherein examiner interpreted enabling and disabling clock generator with a time ratio depending on the temperature difference as the number of steps of the first clock signal and a second clock signal determined by the current temperature control state, wherein examiner interpreted time ratios as the number of steps of first clock signal and the second clock signal).
OH, and CHANG are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to storage devices.
Therefore, before the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above dynamic temperature control method, as taught by OH, and incorporating a clock generator, as taught by CHANG.
One of ordinary skill in the art would have been motivated to improve efficiently controlling non-volatile memory as suggested by CHANG (see Paragraph [0005-0007]).
Regarding claim 12, OH, and CHANG teaches all of the features with respect to claim 11 as outlined above.
CHANG further teaches wherein the number of steps of the first clock signal and the second clock signal represent frequency division ratios of the first clock signal and the second clock signal (Paragraph [0027] “To summarize, in response to the sensed temperature Ts exceeding the first critical temperature TMTU, the controller 104 adjusts a time ratio of enabling the first clock Clk1 and the second clock Clk2 according to the magnitude that the sensed temperature Ts exceeds the first critical temperature TMTU”, Paragraph [0022] “The frequency of the second clock Clk2 is lower than that of the first clock Clk1. For example, the first clock Clk1 may be as high as 1000 MHz or more, while the second clock Clk2 may be only tens of MHz”, wherein examiner interpreted time ratio of enabling first and second clock as the number of steps of the first clock signal and the second clock signal representing frequency division ratios of the first clock signal and the second clock signal).
Regarding claim 13, OH, and CHANG teaches all of the features with respect to claim 11 as outlined above.
CHANG further teaches wherein the number of steps of the first clock signal and the second clock signal represent frequency reduction ratios of the first clock signal and the second clock signal (FIG. 3 illustrates temperature modulation control in accordance with an exemplary embodiment. In this example, in addition to the first critical temperature TMTU for initiating the adaptive cooling strategy, a second critical temperature TM_L and a third critical temperature TM_H are introduced, where TM_L<TM_H<TMTU. In response to the sensed temperature Ts exceeding the second critical temperature TM_L but not exceeding the third critical temperature TM_H, the controller 104 performs a first-level underclocking based on the first clock Clk1 generated by the first clock generator 106. Thus, the flash memory 102 is operated at a frequency reduction rate of N1, where N1 is a number less than 100. For example, the (100-N1) % frequency of the first clock Clk1 is used to create a third clock Clk3 to operate the flash memory 102”, and Paragraph [0031] “The controller 104 alternately enables and disables the first clock generator 106 in an adaptive ratio, to alternately switching between the normal transmission state St and the cooling state Sc in the adaptive ratio”, wherein examiner interpreted memory being operated at a frequency reduction rate based on clock signal enabling and disabling clock generator in an adaptive ratio as the number of steps of the first clock signal and the second clock signal represent frequency reduction ratios of the first clock signal and the second clock signal, and Paragraph [0032]).
Claims 7-8, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. USPGPUB 2016/0306592 (hereinafter “OH”), in view of Yang et al. USPGPUB 2022/0334940 (hereinafter “Yang”).
Regarding claim 7, OH teaches all of the features with respect to claim 1 as outlined above.
OH does not explicitly teach wherein: the dynamic temperature control mechanism further comprises a state increment table; the controller is configured to determine whether a current state value corresponding to the current temperature control state is a maximum value; when the controller determines that the current state value is not equal to the maximum value, the controller is further configured to determine a state value increment with reference to the state value increment table according to the temperature accumulation value; and the controller is further configured to update the current state value by adding the state value increment to the current state value, and reset the temperature accumulation value.
However, Yang teaches wherein: the dynamic temperature control mechanism further comprises a state increment table (Paragraph [0023] “the controller 100 may store a plurality of performance tables therein. Here, the performance tables may each include a plurality of entries each including information regarding operation performance (i.e., an operation performance level) of the non-volatile memory device 200. In some embodiments, the information regarding the operation performance may include a clock speed of a clock at which the non-volatile memory device 200 operates. The controller 100 may control the operation of the non-volatile memory device 200 based on the performance tables and a first temperature T1 measured by the first temperature sensor 310 and a second temperature T2 measured by the second temperature sensor 320, which will be described later”, wherein examiner interpreted performance tables including information regarding operation performance of non-volatile memory as the dynamic temperature control mechanism further comprises a state increment table);
the controller is configured to determine whether a current state value corresponding to the current temperature control state is a maximum value (Paragraph [0060] “in P121 to P126, a difference ΔT between the first temperature T1 and the second temperature T2 may be compared with set ranges. According to example embodiments, the controller 100 may select one of a plurality of performance tables (e.g., first to sixth performance tables) based on the difference ΔT”, wherein examiner interpreted temperature difference compared with set ranges as determining whether a current state value corresponding to the current temperature control state is a maximum value);
when the controller determines that the current state value is not equal to the maximum value (FIG. 5, Paragraph [0060] “Next, in P121 to P126, a difference ΔT between the first temperature T1 and the second temperature T2 may be compared with set ranges. According to example embodiments, the controller 100 may select one of a plurality of performance tables (e.g., first to sixth performance tables) based on the difference ΔT”, wherein examiner interpreted determining that the difference of temperatures is not within the ranges specified for each P121-P126 as controller determining that the current state value is not equal to the maximum value), the controller is further configured to determine a state value increment with reference to the state value increment table according to the temperature accumulation value (FIG. 5, Paragraphs [0061-0066], and Paragraphs [0067-0068], wherein examiner interpreted one of the rangers not being satisfied and then satisfying one of the ranges which leads to applying its respective performance tables as controller configured to determine a state value increment with reference to the state value increment table according to the temperature accumulation value, wherein examiner interpreted performance table having different performance control entering temperature that changes the higher the temperature difference as incrementing state value with reference to the state value increment table according to the temperature accumulation value); and
the controller is further configured to update the current state value by adding the state value increment to the current state value, and reset the temperature accumulation value (Paragraph [0069-0074], FIG. 5, wherein examiner interpreted performance of storage device being limited according to the performance table as updating the current state value by adding the state value increment to the current state value, wherein examiner interpreted maintaining maximum operation of the storage device as adding state value increment to the current state value, and wherein examiner interpreted monitoring temperature and comparing temperature as to include resetting temperature accumulation value).
OH, and Yang are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to storage devices.
Therefore, before the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above solid-state storage device, as taught by OH, and incorporating state increment table, as taught by Yang.
One of ordinary skill in the art would have been motivated to improve operating memory at high performance to reduce temperature rise so that malfunction, or damage to the internal devices of the system may be prevented, as suggested by Yang (see Paragraph [0004], and Paragraphs [0069-0074]).
Regarding claim 8, OH, and Yang teaches all of the features with respect to claim 7 as outlined above.
Yang further teaches wherein: the dynamic temperature control mechanism further comprises a state value decrement table (Paragraph [0023] “the controller 100 may store a plurality of performance tables therein. Here, the performance tables may each include a plurality of entries each including information regarding operation performance (i.e., an operation performance level) of the non-volatile memory device 200. In some embodiments, the information regarding the operation performance may include a clock speed of a clock at which the non-volatile memory device 200 operates. The controller 100 may control the operation of the non-volatile memory device 200 based on the performance tables and a first temperature T1 measured by the first temperature sensor 310 and a second temperature T2 measured by the second temperature sensor 320, which will be described later”, wherein examiner interpreted performance tables including information regarding operation performance of non-volatile memory as the dynamic temperature control mechanism further comprises a state value decrement table);
when the controller determines that the current state value is the maximum value, the controller is further configured to determine a state value decrement with reference to the state value decrement table according to the temperature accumulation value (FIG. 5, Paragraphs [0060-0066], and Paragraphs [0067-0068], wherein examiner interpreted determining whether temperature difference is within a range as determining that current state value is the maximum value, and wherein examiner interpreted determining the performance table to apply based on temperature difference being within the threshold as determining that a state value decrement with reference to the state value decrement table according to the temperature accumulation value); and
the controller is further configured to update the current state value by subtracting the state value decrement from the current state value, and reset the temperature accumulation value (Paragraph [0069-0074], FIG. 5, wherein examiner interpreted limiting performance of the storage device when temperature reaches its respective performance control entering temperature as updating the current state value by subtracting the state value decrement from the current state value, and reset the temperature accumulation value, and examiner interpreted monitoring temperature and comparing temperature as to include resetting temperature accumulation value).
Regarding claim 15, OH teaches all of the features with respect to claim 9 as outlined above.
OH does not explicitly teach wherein the dynamic temperature control mechanism further comprises a state increment table, and the method further comprises: utilizing the controller to determine whether a current state value corresponding to the current temperature control state is a maximum value; when the controller determines that the current state value is not equal to the maximum value, utilizing the controller to determine a state value increment with reference to the state value increment table according to the temperature accumulation value; and utilizing the controller to update the current state value by adding the state value increment to the current state value, and to reset the temperature accumulation value.
However, Yang teaches wherein the dynamic temperature control mechanism further comprises a state increment table (Paragraph [0023] “the controller 100 may store a plurality of performance tables therein. Here, the performance tables may each include a plurality of entries each including information regarding operation performance (i.e., an operation performance level) of the non-volatile memory device 200. In some embodiments, the information regarding the operation performance may include a clock speed of a clock at which the non-volatile memory device 200 operates. The controller 100 may control the operation of the non-volatile memory device 200 based on the performance tables and a first temperature T1 measured by the first temperature sensor 310 and a second temperature T2 measured by the second temperature sensor 320, which will be described later”, wherein examiner interpreted performance tables including information regarding operation performance of non-volatile memory as the dynamic temperature control mechanism further comprises a state increment table), and the method further comprises:
utilizing the controller to determine whether a current state value corresponding to the current temperature control state is a maximum value (Paragraph [0060] “in P121 to P126, a difference ΔT between the first temperature T1 and the second temperature T2 may be compared with set ranges. According to example embodiments, the controller 100 may select one of a plurality of performance tables (e.g., first to sixth performance tables) based on the difference ΔT”, wherein examiner interpreted temperature difference compared with set ranges as determining whether a current state value corresponding to the current temperature control state is a maximum value);
when the controller determines that the current state value is not equal to the maximum value (FIG. 5, Paragraph [0060] “Next, in P121 to P126, a difference ΔT between the first temperature T1 and the second temperature T2 may be compared with set ranges. According to example embodiments, the controller 100 may select one of a plurality of performance tables (e.g., first to sixth performance tables) based on the difference ΔT”, wherein examiner interpreted determining that the difference of temperatures is not within the ranges specified for each P121-P126 as controller determining that the current state value is not equal to the maximum value), utilizing the controller to determine a state value increment with reference to the state value increment table according to the temperature accumulation value (FIG. 5, Paragraphs [0061-0066], and Paragraphs [0067-0068], wherein examiner interpreted one of the rangers not being satisfied and then satisfying one of the ranges which leads to applying its respective performance tables as controller configured to determine a state value increment with reference to the state value increment table according to the temperature accumulation value, wherein examiner interpreted performance table having different performance control entering temperature that changes the higher the temperature difference as incrementing state value with reference to the state value increment table according to the temperature accumulation value); and
utilizing the controller to update the current state value by adding the state value increment to the current state value, and to reset the temperature accumulation value (Paragraph [0069-0074], FIG. 5, wherein examiner interpreted performance of storage device being limited according to the performance table as updating the current state value by adding the state value increment to the current state value, wherein examiner interpreted maintaining maximum operation of the storage device as adding state value increment to the current state value, and wherein examiner interpreted monitoring temperature and comparing temperature as to include resetting temperature accumulation value).
OH, and Yang are analogous art because they are from the same field of endeavor and contain overlapping structural and functional similarities. They both relate to storage devices.
Therefore, before the time of effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the above solid-state storage device, as taught by OH, and incorporating state increment table, as taught by Yang.
One of ordinary skill in the art would have been motivated to improve operating memory at high performance to reduce temperature rise so that malfunction, or damage to the internal devices of the system may be prevented, as suggested by Yang (see Paragraph [0004], and Paragraphs [0069-0074]).
Regarding claim 16, OH, and Yang teaches all of the features with respect to claim 15 as outlined above.
Yang further teaches wherein the dynamic temperature control mechanism further comprises a state value decrement table (Paragraph [0023] “the controller 100 may store a plurality of performance tables therein. Here, the performance tables may each include a plurality of entries each including information regarding operation performance (i.e., an operation performance level) of the non-volatile memory device 200. In some embodiments, the information regarding the operation performance may include a clock speed of a clock at which the non-volatile memory device 200 operates. The controller 100 may control the operation of the non-volatile memory device 200 based on the performance tables and a first temperature T1 measured by the first temperature sensor 310 and a second temperature T2 measured by the second temperature sensor 320, which will be described later”, wherein examiner interpreted performance tables including information regarding operation performance of non-volatile memory as the dynamic temperature control mechanism further comprises a state value decrement table), and the method further comprises:
when the controller determines that the current state value is the maximum value, utilizing the controller to determine a state value decrement with reference to the state value decrement table according to the temperature accumulation value (FIG. 5, Paragraphs [0060-0066], and Paragraphs [0067-0068], wherein examiner interpreted determining whether temperature difference is within a range as determining that current state value is the maximum value, and wherein examiner interpreted determining the performance table to apply based on temperature difference being within the threshold as determining that a state value decrement with reference to the state value decrement table according to the temperature accumulation value); and
utilizing the controller to update the current state value by subtracting the state value decrement from the current state value, and to reset the temperature accumulation value (Paragraph [0069-0074], FIG. 5, wherein examiner interpreted limiting performance of the storage device when temperature reaches its respective performance control entering temperature as updating the current state value by subtracting the state value decrement from the current state value, and reset the temperature accumulation value, and examiner interpreted monitoring temperature and comparing temperature as to include resetting temperature accumulation value).
Citation of Pertinent Prior Art
The prior art made of record and on the attached PTO Form 892 but not relied upon is considered pertinent to applicant's disclosure.
LEE et al. [USPGPUB 2023/0176788] teaches a memory controller configured having a plurality of operation commands defined for different temperature and an external temperature sensor.
Hsu et al. [USPGPUB 2022/0214828] teaches a storage device management method for a storage device.
Yang et al. [USPGPUB 2019/0138224] teaches a high-temperature protection method for a solid state drive (SSD) and an implementation device thereof.
Conclusion
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/D.P./Examiner, Art Unit 2119 /MOHAMMAD ALI/Supervisory Patent Examiner, Art Unit 2119
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