Prosecution Insights
Last updated: October 01, 2026
Application No. 18/678,584

SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §103§112
Filed
May 30, 2024
Priority
Jun 27, 2022 — JP 2022-102873 +1 more
Examiner
WEILAND, ADAM DAVID
Art Unit
Tech Center
Assignee
Fuji Electric Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
38 granted / 40 resolved
+35.0% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
37 currently pending
Career history
92
Total Applications
across all art units

Statute-Specific Performance

§103
54.3%
+14.3% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 40 resolved cases

Office Action

§103 §112
DETAILED ACTION This action is responsive to the communication filed 4 August 2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Election/Restrictions Applicant’s election without traverse of the Group I Species 1 (FIG. 5) embodiment is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation "the resin case.” There is insufficient antecedent basis for this limitation in the claim. Claims 6 and 8, which depend from claim 5, are rejected under § 112(b) for the same reasons as claim 5. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2021/0202372 (published July 1, 2021) (hereinafter “Kato”) in view of Japanese Patent Publication No. JPH10303349A (published Nov. 13, 1998) (hereinafter “Yoneda”). Regarding independent claim 1, Kato discloses: A semiconductor module, comprising: a resin case (FIG. 11, case 21 formed from resin, [0025]); an insulating sheet having a first surface and a second surface opposite to the first surface (FIG. 11, insulating sheets 23/41 having lower and upper surfaces which may be “first” and “second” surfaces, respectively, that are opposite to each other, [0054]), the insulating sheet extending from inside the resin case to outside (FIG. 11, depicting wherein the insulating sheets 23/41 extend from inside the case 21 to outside the case 21); a first terminal extending from inside the resin case to the outside (FIG. 11, terminal 22 extending from inside the case to outside the case, [0025]), the first terminal being disposed on the first surface of the insulating sheet, except for a tip portion thereof that is spaced apart from the first surface in a thickness direction perpendicular to the first surface (FIG. 11, depicting wherein the terminal 22 is disposed on the first surface, except for a tip portion thereof that is spaced apart from the first surface in a thickness direction perpendicular to the first surface), the first terminal overlapping the insulating sheet in a plan view of the semiconductor module (FIGS. 2/11, depicting wherein the terminal 22 overlaps the insulating sheets 23/41 in the plan view), the tip portion of the first terminal being a first tip portion (FIG. 11, depicting wherein the terminal 22 has a tip portion which may be a “first” tip portion); and a second terminal extending from inside the resin case to the outside (FIG. 11, depicting terminal 24 and coupling member 40, [0025], [0038]), the second terminal being disposed on the second surface of the insulating sheet, except for a tip portion thereof that is spaced apart from the second surface in the thickness direction (FIG. 11, depicting wherein the terminal 24 and coupling member 40 are disposed on the second surface, except for a tip portion thereof that is spaced apart from the second surface in a thickness direction perpendicular to the second surface), the second terminal overlapping the insulating sheet and the first terminal in the plan view (FIGS. 1/2/11, depicting wherein the terminal 24 and coupling member 40 overlap the insulating sheets 23 and 41 and terminal 22 in the plan view), the tip portion of the second terminal being a second tip portion (FIG. 11, depicting wherein the terminal 24 and coupling member 40 has a tip portion which may be a “second” tip portion). Kato does not specifically disclose wherein the insulating sheet extends further outside than both the first tip portion and the second tip portion. In the same field of endeavor, Yoneda discloses a semiconductor device including insulating sheets and a configuration of first and second terminals having tip portions (FIGS. 1-4,9, insulating sheets 16/26/116/117/123, conductors 11/12//21/22/111/112/121/122, and terminals 14/15/24/25/114/115/124/125, [0021]-[0023], [0008]-[0009]). Regarding the configuration of the tip portions of the terminals, in [0008], Yoneda states: “The terminals 114 and 115 are provided between the flat conductors 111 and 112 so that other parts such as a snubber capacitor and an electrolytic capacitor, or other circuits can be easily connected from the outside to one of the flat conductors 111 and 112.” Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Kato by substituting the terminal configuration of Yoneda in order to allow for easy connection between the conductors and other outside conductors as disclosed in Yoneda. See Yoneda [0008]. Moreover, substitution of the terminal configuration of Yoneda would result in a configuration wherein the insulating sheets 22/41 extend further outside than the first tip portion and the second tip portion of the terminal 21 and terminal 24 and coupling member 40. Regarding claim 2, Kato in view of Yoneda further discloses wherein the first tip portion and the second tip portion overlap each other in the plan view (Kato FIGS. 2/11; Yoneda FIGS. 1-4/9; depicting wherein the first and second tip portions would overlap each other in the plan view). Regarding claim 3, Kato in view of Yoneda further discloses wherein the first terminal further includes a first extending portion extending from inside the resin case to the first tip portion and being in contact with the first surface (FIGS. 2/11, depicting wherein the terminal 22 includes a portion extending from inside the case 21, and which is in contact with the first surface of the insulating sheets 23/41), and the second terminal further includes a second extending portion extending from inside the resin case to the second tip portion and being in contact with the second surface (FIGS. 2/11, depicting wherein the terminal 24 and coupling member 40 includes a portion extending from inside the case 21, and which is in contact with the second surface of the insulating sheets 23/41). Regarding claim 4, Kato in view of Yoneda further discloses wherein the resin case includes a terrace portion on which the first terminal, the second terminal, and the insulating sheet are disposed (FIGS. 2/11, depicting wherein the case 21 includes a terrace portion on which the terminal 22, terminal 24 and coupling member 40, and insulating sheets 23/41 are disposed), and a pressing portion pressing the first terminal, the second terminal, and the insulating sheet disposed against the terrace portion (FIG. 2, depicting storage areas 21c pressing the terminal 22, terminal 24 and coupling member 40, and insulating sheets 23/41 against the terrace portion). Regarding independent claim 5, Kato discloses: A semiconductor device, comprising: a semiconductor module, including an insulating sheet having a first surface and a second surface opposite to the first surface (FIG. 11, insulating sheets 23/41 having lower and upper surfaces which may be “first” and “second” surfaces, respectively, that are opposite to each other, [0054]), the insulating sheet extending from inside the resin case to outside (FIG. 11, depicting wherein the insulating sheets 23/41 extend from inside the case 21 to outside the case 21); a first terminal extending from inside the resin case to the outside (FIG. 11, terminal 22 extending from inside the case to outside the case, [0025]), the first terminal being disposed on the first surface of the insulating sheet, except for a tip portion thereof that is spaced apart from the first surface in a thickness direction perpendicular to the first surface (FIG. 11, depicting wherein the terminal 22 is disposed on the first surface, except for a tip portion thereof that is spaced apart from the first surface in a thickness direction perpendicular to the first surface), the first terminal overlapping the insulating sheet in a plan view of the semiconductor module (FIGS. 2/11, depicting wherein the terminal 22 overlaps the insulating sheets 23/41 in the plan view), the tip portion of the first terminal being a first tip portion (FIG. 11, depicting wherein the terminal 22 has a tip portion which may be a “first” tip portion); and a second terminal extending from inside the resin case to the outside (FIG. 11, depicting terminal 24 and coupling member 40, [0025], [0038]), the second terminal being disposed on the second surface of the insulating sheet, except for a tip portion thereof that is spaced apart from the second surface in the thickness direction (FIG. 11, depicting wherein the terminal 24 and coupling member 40 are disposed on the second surface, except for a tip portion thereof that is spaced apart from the second surface in a thickness direction perpendicular to the second surface), the second terminal overlapping the insulating sheet and the first terminal in the plan view (FIGS. 1/2/11, depicting wherein the terminal 24 and coupling member 40 overlap the insulating sheets 23 and 41 and terminal 22 in the plan view), the tip portion of the second terminal being a second tip portion (FIG. 11, depicting wherein the terminal 24 and coupling member 40 has a tip portion which may be a “second” tip portion), a capacitor including two terminals (FIG. 11, depicting wherein the capacitor 30 includes two terminals, 32/34b, [0033]), tip portions thereof being respectively: a third tip portion connected to the first tip portion and spaced apart from the first surface in the thickness direction (FIG. 11, depicting wherein the terminal 32 has a tip portion that may be a “third” tip portion), and a fourth tip portion connected to the second tip portion and being spaced apart from the second surface in the thickness direction (FIG. 11, depicting wherein the terminal 34b has a tip portion that may be a “fourth” tip portion). Kato does not specifically disclose wherein the insulating sheet extends further outside than both the first tip portion and the second tip portion. In the same field of endeavor, Yoneda discloses a semiconductor device including insulating sheets and a configuration of first and second terminals having tip portions (FIGS. 1-4,9, insulating sheets 16/26/116/117/123, conductors 11/12//21/22/111/112/121/122, and terminals 14/15/24/25/114/115/124/125, [0021]-[0023], [0008]-[0009]). Regarding the configuration of the tip portions of the terminals, in [0008], Yoneda states: “The terminals 114 and 115 are provided between the flat conductors 111 and 112 so that other parts such as a snubber capacitor and an electrolytic capacitor, or other circuits can be easily connected from the outside to one of the flat conductors 111 and 112.” Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of Kato by substituting the terminal configuration of Yoneda in order to allow for easy connection between the conductors and other outside conductors as disclosed in Yoneda. See Yoneda [0008]. Moreover, substitution of the terminal configuration of Yoneda would result in a configuration wherein the insulating sheets 22/41 extend further outside than the first tip portion and the second tip portion of the terminal 21 and terminal 24 and coupling member 40. Regarding claim 6, Kato in view of Yoneda further discloses wherein the first tip portion and the third tip portion are connected without overlapping each other in the plan view, and the second tip portion and the fourth tip portion are connected without overlapping each other in the plan view (Kato FIGS. 2/11; Yoneda FIGS. 1-4/9; depicting wherein the first and third tip portions would be connected without overlapping in the plan view, and the second and fourth tip portions would be connected without overlapping in the plan view). Regarding claim 8, Kato in view of Yoneda further discloses wherein the first tip portion and the third tip portion have a first welding area therebetween (Kato FIGS. 2/11; Yoneda FIGS. 1-4/9, depicting wherein the first and third tip portions would include bonding areas 221 therebetween, wherein the bonding areas may be where welding is performed, [0044]), and the second tip portion and the fourth tip portion have a second welding area therebetween (Kato FIGS. 2/11; Yoneda FIGS. 1-4/9, depicting wherein the second and fourth tip portions would include bonding areas 343 therebetween, wherein the bonding areas may be where welding is performed, [0044]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2021/0308791 (filed Aug. 23, 2019) (disclosing a terminal configuration similar to that claimed by applicant); 2018/0084661 (filed Sept. 19, 2016) (disclosing a terminal and insulating sheet configuration similar to that claimed by applicant). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADAM D WEILAND/Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

May 30, 2024
Application Filed
Sep 18, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
99%
With Interview (+8.0%)
3y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 40 resolved cases by this examiner. Grant probability derived from career allowance rate.

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