DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been cancelled and claims 21-40 are pending for examination. Claims 21, 27, and 34 are independent claims. This Office Action is Non-Final.
Information Disclosure Statement
The information disclosure statement filed 07/23/2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of Non-patent literature document Cite No. 2 “Office Action mailed June 29, 2025 for Chinese Application No. 202380044719.2” (lined through) that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered. The remaining references in the IDS that are not lined through have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 39 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 39, line 1 and also line 2 “the check values” is not clear if refers to claim 38, lines 2-3 “…corresponding check value” or claim 34, line 2 “…corresponding check value”? Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 38-39 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 38 depends on claim 34 and recites limitation of same scope “generating, for each write portion of the plurality of write portions, a corresponding check value” as claim 34, lines 2-3 and therefore fails to further limit the subject matter of the claim upon which it depends. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Claim 39 depends on claim 38 and inherits the deficiencies of claim 38. Applicant may cancel the claim, amend the claim to place the claim in proper dependent form, rewrite the claim in independent form, or present a sufficient showing that the dependent claim complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 34-35, 37-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7, 17-19 of U.S. Patent No. 12,013,752 (reference application). Although the Instant Application claims 34-35, 37-40 and Patent No. 12,013,752 claims 7, 17-19 at issue are not identical, they are not patentably distinct from each other because, as shown in the table below, Instant Application claims 34-35, 37-40 are anticipated by Patent No. 12,013,752 claims 7, 17-19.
Instant Application
18/678,596
U.S. Patent No. 12,013,752
34. A method, comprising:
generating a corresponding check value for each write portion of a plurality of write portions each identifying a respective portion of data to be written to
a stacked memory; and
writing, to the stacked memory, the plurality of write portions, corresponding check values, and write parity data, wherein the write parity data is based on the respective portions of data to be written to the stacked memory identified by each write portion of the plurality of write portions.
Claim 17. A method comprising:
generating, at a processing device, a check value for each write portion of a plurality of write portions based on an error correction code implemented by the processing device, each write portion of the plurality of write portions identifying a respective portion of data to be written to a memory; …
Claim 18. The method of claim 17, wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
Claim 17 (Con’t)
…determining a write parity based on the respective portions of data to be written to the memory of each write portion of the plurality of write portions and an operation; and
sending, to the memory, the write portions, check values, and write parity.
35. The method of claim 34, further comprising:
sending a first write portion of the plurality of write portions to the stacked memory by a first pseudo channel of the stacked memory; and
sending a second write portion of the plurality of write portions to the stacked memory by a second pseudo channel of the stacked memory.
Claim 19
37. The method of claim 34, further comprising:
generating the write parity data based on one or more operations and the plurality of write portions.
Claim 17
38. The method of claim 34, further comprising:
generating, for each write portion of the plurality of write portions, a corresponding check value.
Claim 17
39. The method of claim 38, wherein generating the check values comprises generating the check values using an on-die error correction code implemented by the stacked memory.
Claim 7
40. The method of claim 34, wherein the stacked memory comprises a three- dimensional stacked synchronous dynamic random-access memory.
Claim 18
With regards to claims 34-35, 37-40 of the Instant Application, claims 7, 17-19 of U.S. Patent No. 12,013,752 is in essence a “species” of the generic invention of Instant Application claims 34-35, 37-40. It has been held that a generic invention is “anticipated” by a “species” within the scope of the generic invention. See In re Goodman, 29 USPQ2d 2010 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21, 24-25, 27-30, 32, 34, 37-39 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Criss et al. (U.S. Patent Publn No. 2019/0042358 A1, cited in IDS), hereinafter Criss.
Regarding claim 21, Criss teaches (in bold):
A processing device (Criss, Fig. 1 and Fig. 11, Abstract, paragraph 0019-0022), comprising:
one or more processor cores (Criss, Fig. 11, paragraph 0057, processing component 1108, paragraph 0058 “one or more processors, multi-core processors”) configured to:
generate a corresponding check value (Under BRI as recited in applicant’s originally filed specification in paragraph 0022, interpreting ECC or CRC codes (e.g. CRC-9, CRC-12, CRC-16), symbol-based codes … or binary convolution codes and so on as a type of check value, see MPEP 2111.01(V). Criss in the Abstract teaches “memory controller ECC check bits”. See also Fig. 7, block 708, paragraph 0048 “At block 708, the memory controller sends the data bits, the memory controller ECC check bits, and the parity bit(s) to memory device 102.”) for each write portion of a plurality of write portions (Criss, Fig. 7, block 702, paragraph 0048 “write operation for memory controller 104 … At block 702, memory controller 104 receives data bits to write to memory device 102 over cache lines as is known in the computer arts…. the number of data bits received may be 512, although in other computing platforms other amounts may be received, such as 8, 16, 32, 64, 128, 256, 1024 and so on.” See also plurality of data bits shown in Figs. 3 and 4 paragraph 0026 “HBM3 ½ cache-line bit layout”), each write portion of the plurality of write portions identifying a corresponding portion of data to be written to a memory (Criss, Figs. 3-4, write portions DQ0-DQ39 correspond to each line 302-316, and B0-B31 are data to be written to a memory. See also paragraph 0026 “32 bits of data 318, denoted bit B0 through bit B31”); and
write the data identified by the plurality of write portions, corresponding check values of the plurality of write portions, and write parity data to the memory (Criss, Fig. 7, block 708 “Send data bits, memory controller ECC check bits and parity bit(s) to memory device”. See paragraph 0048 “At block 708, the memory controller sends the data bits, the memory controller ECC check bits, and the parity bit(s) to memory device 102.”), the write parity data based on the corresponding portions of the data identified by the plurality of write portions (Criss, Fig. 7, “At block 704, memory controller 104, using memory controller ECC component 114, determines a plurality of memory controller ECC check bits and one or more parity bit(s) for the received data bits.”).
Regarding claim 24, the rejection of claim 21 is incorporated as given above. Criss teaches wherein the one or more processor cores are configured to:
generate the write parity data based on one or more operations and the plurality of write portions (Criss, Fig. 3 and Fig. 4 and parity 322 for each write portion 302, 304, … 316, a parity is calculated for plurality of write portions. Paragraphs 0026-0029 and 0032-0035 teaches equation with an operation that is XOR operation).
Regarding claim 25, the rejection of claim 24 is incorporated as given above. Criss teaches wherein the one or more operations include a XOR operation (Criss, Paragraphs 0026-0029 and 0032-0035 teaches XOR operation).
Regarding claim 27, Criss teaches:
A processing device (Criss, Fig. 1 and Fig. 11, Abstract, paragraph 0019-0022), comprising:
one or more processor cores (Criss, Fig. 11, paragraph 0057, processing component 1108, paragraph 0058 “one or more processors, multi-core processors”) configured to:
based on a check bit indicating a fetch return of a plurality of fetch returns includes a fault (Criss, Fig. 2, paragraph 0022-0023 “to avoid on-die ECC miss-correction by providing parity conditions to on-die ECC component 110 that may be checked to ascertain if a multi-bit error is present and halt on-die ECC correction when multi-bit errors are present. …data and on-die ECC check bits 202 may be read out of memory 112….On-die ECC component 110 may detect and correct errors in the data based on analyzing the on-die ECC check bits to generate single error correcting code (SEC) data 204.” See also plurality of data bits shown in Figs. 3 and 4 paragraph 0026 “HBM3 ½ cache-line bit layout”), reconstruct the fetch return based on parity fetch data associated with the plurality of fetch returns and based on one or more other fetch returns of the plurality of fetch returns (Criss, Fig. 3 shows a data layout of HBM3 ½ cache line with multiple bursts BLO-BL7 and parity 322 for each burst P0-P7. Parity is shown calculated for P0 in paragraph 0027 and similarly for P1-P7. Fig. 2, paragraphs 0023-0024 teaches “On-die ECC component 110 may detect and correct errors in the data based on analyzing the on-die ECC check bits to generate single error correcting code (SEC) data 204. However, miss-correction of errors may be introduced by on-die ECC component 110. Memory controller ECC component 114 detects and corrects these miss-corrections and produces corrected data 206. …For example, a bit-wise parity over all bursts of data signaled over I/O data lines from memory 112 may be appended to the data as part of the external ECC code.”).
Regarding claim 28, the rejection of claim 27 is incorporated as given above. Criss teaches wherein the one or more processor cores are configured to:
divide a fetch request identifying data to be fetched from a memory into a plurality of fetch portions based on a number of channels of the memory (Criss, Fig. 7, block 702, paragraph 0048 “the number of data bits received may be 512, although in other computing platforms other amounts may be received, such as 8, 16, 32, 64, 128, 256, 1024 and so on.” See also plurality of data bits shown in Figs. 3 and 4 paragraph 0026 “HBM3 ½ cache-line bit layout” Fig. 3 shows 256 bits split up into 8 bursts BL0 …BL7. Paragraph 0026 teaches “this data layout may be used for data and external ECC check and parity bits, or metadata bits. … Each burst comprises a signaling of data over I/O data lines (e.g., cache lines) between memory device 102 and memory controller 104. Each I/O data line may be known as a DQ, numbered from DQ0 to DQ39 for a transfer of 40 bits of information. In this example, burst BL0 302 comprises 32 bits of data 318….” As Criss teaches 512 data bits in paragraph 0048 and DQ0 to DQ31 are data lines that form 256 bit implementation shown in Fig. 3 and explained in paragraph 0026, Criss teaches 2 channels each of 32 bits and plurality of fetch portions of bursts BL0 to BL7), wherein each fetch portion of the plurality of fetch portions identifies a corresponding portion of the data to be fetched from the memory (Criss, Fig. 3, HBM3 ½ cache-line bit layout for first channel B0 ...B31, B32…B63, …B224..B255 for each separate bursts BL0 to BL7 and Fig. 10, paragraph 0055 teaches “read operation for memory controller 104. At block 1002, memory controller 104 receives data bits and the memory controller ECC check bits from memory device 102. … At block 1006, the memory controller returns the data bits to the computer platform component requesting the data.”).
Regarding claim 29, the rejection of claim 28 is incorporated as given above. Criss teaches wherein the one or more processor cores are configured to divide the fetch request into the plurality of fetch portions further based on one or more widths of channels of the number of channels of the memory (Criss, Fig. 3, plurality of data bits shown in Figs. 3 and 4 paragraph 0026 “HBM3 ½ cache-line bit layout” Fig. 3 shows 256 bits split up into 8 bursts BL0 …BL7. Paragraph 0026 teaches “this data layout may be used for data and external ECC check and parity bits, or metadata bits. … Each burst comprises a signaling of data over I/O data lines (e.g., cache lines) between memory device 102 and memory controller 104. Each I/O data line may be known as a DQ, numbered from DQ0 to DQ39 for a transfer of 40 bits of information. In this example, burst BL0 302 comprises 32 bits of data 318….” As Criss teaches 512 data bits in paragraph 0048 and DQ0 to DQ31 are 32 data lines that form 256 bit implementation shown in Fig. 3 and explained in paragraph 0026, Criss teaches 2 channels each of 32 bits and plurality of fetch portions of bursts BL0 to BL7).
Regarding claim 30, the rejection of claim 28 is incorporated as given above. Criss teaches wherein the one or more processor cores are configured to:
send, to the memory, the plurality of fetch portions (Criss, Fig. 3, HBM3 ½ cache-line bit layout for first channel B0 ...B31, B32…B63, …B224..B255 for each separate bursts BL0 to BL7 and the request to memory for fetch portions is taught in Fig. 9, paragraph 0050 teaches “At block 902, when reading data from the memory device is requested, memory device 102 gets the data bits, the memory controller ECC check bits, and the on-die ECC check bits from memory 112.”); and
send, to the memory, a parity request identifying the plurality of fetch portions and one or more operations (Criss, Fig. 3 and paragraph 0026 “Each burst comprises a signaling of data over I/O data lines (e.g., cache lines) between memory device 102 and memory controller 104. … In this example, burst BL0 302 comprises 32 bits of data 318, denoted bit B0 through bit B31, external ECC check bits, additional parity bits, or metadata bits 320 comprises seven bits, denoted bit E0 through bit E6, and parity bit 322 comprises one bit, denoted bit P0. The parity bit for burst BL0 302 may be the bit-wise XOR of all bits in the burst from DQ0 to DQ38 (becoming bit 0 through bit 38 (i.e., B0 to B31 and E0 to E6).” Paragraph 0050 teaches in each request requesting data bits, memory controller ECC check bits and one or more parity bits (on-die ECC check bit)).
Regarding claim 32, the rejection of claim 28 is incorporated as given above. Criss teaches wherein the parity fetch data is based on the corresponding portions of the data identified by the plurality of fetch portions and one or more operations (Criss, Fig. 3 and paragraph 0026 “Each burst comprises a signaling of data over I/O data lines (e.g., cache lines) between memory device 102 and memory controller 104. … In this example, burst BL0 302 comprises 32 bits of data 318, denoted bit B0 through bit B31, external ECC check bits, additional parity bits, or metadata bits 320 comprises seven bits, denoted bit E0 through bit E6, and parity bit 322 comprises one bit, denoted bit P0. The parity bit for burst BL0 302 may be the bit-wise XOR of all bits in the burst from DQ0 to DQ38 (becoming bit 0 through bit 38 (i.e., B0 to B31 and E0 to E6).” Paragraph 0050 teaches in each request requesting data bits, memory controller ECC check bits and one or more parity bits (on-die ECC check bit)).
Regarding claim 34, Criss teaches:
A method, comprising:
generating a corresponding check value (Under BRI as recited in applicant’s originally filed specification in paragraph 0022, interpreting ECC or CRC codes (e.g. CRC-9, CRC-12, CRC-16), symbol-based codes … or binary convolution codes and so on as a type of check value, see MPEP 2111.01(V). Criss in the Abstract teaches “memory controller ECC check bits”. See also Fig. 7, block 708, paragraph 0048 “At block 708, the memory controller sends the data bits, the memory controller ECC check bits, and the parity bit(s) to memory device 102.”) for each write portion of a plurality of write portions (Criss, Fig. 7, block 702, paragraph 0048 “write operation for memory controller 104 … At block 702, memory controller 104 receives data bits to write to memory device 102 over cache lines as is known in the computer arts…. the number of data bits received may be 512, although in other computing platforms other amounts may be received, such as 8, 16, 32, 64, 128, 256, 1024 and so on.” See also plurality of data bits shown in Figs. 3 and 4 paragraph 0026 “HBM3 ½ cache-line bit layout”) each identifying a respective portion of data to be written to a stacked memory (Criss, Figs. 3-4, write portions DQ0-DQ39 correspond to each line 302-316, and B0-B31 are data to be written to a memory. See also paragraph 0026 “32 bits of data 318, denoted bit B0 through bit B31”) (Stacked memory is taught by Chen, page 646, section 1, left column “3D DRAMS, e.g., high bandwidth memory (HBM)”. Section “2.1 3D High Bandwidth Memory Architecture” shows in Fig. 2 3D stacked memory that is clocked/synchronous); and
writing, to the stacked memory, the plurality of write portions, corresponding check values, and write parity data (Criss, Fig. 7, block 708 “Send data bits, memory controller ECC check bits and parity bit(s) to memory device”. See paragraph 0048 “At block 708, the memory controller sends the data bits, the memory controller ECC check bits, and the parity bit(s) to memory device 102.”), wherein the write parity data is based on the respective portions of data to be written to the stacked memory identified by each write portion of the plurality of write portions (Criss, Fig. 7, “At block 704, memory controller 104, using memory controller ECC component 114, determines a plurality of memory controller ECC check bits and one or more parity bit(s) for the received data bits.”).
Regarding claim 38, the rejection of claim 34 is incorporated as given above. Criss teaches generating, for each write portion of the plurality of write portions, a corresponding check value (Under BRI as recited in applicant’s originally filed specification in paragraph 0022, interpreting ECC or CRC codes (e.g. CRC-9, CRC-12, CRC-16), symbol-based codes … or binary convolution codes and so on as a type of check value, see MPEP 2111.01(V). Criss in the Abstract teaches “memory controller ECC check bits”. See also Fig. 7, blocks 704, 708, paragraph 0048 “At block 704, memory controller 104, using memory controller ECC component 114, determines a plurality of memory controller ECC check bits and one or more parity bit(s) for the received data bits….At block 708, the memory controller sends the data bits, the memory controller ECC check bits, and the parity bit(s) to memory device 102.”).
Regarding claim 39, the rejection of claim 38 is incorporated as given above. Criss teaches wherein generating the check values comprises generating the check values using an on-die error correction code implemented by the stacked memory (Criss, Fig. 1, On-Die ECC Component 110 in memory device 102. Fig. 8, block 804, paragraph 0049 teaches “At block 804, memory device 102, using on-die ECC component 110, determines the on-die ECC check bits for the received data bits.”).
Claim 37, the method that implements the apparatus of claim 24 is rejected on the same grounds as claim 24.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22-23, 26, 31, 33, 35-36, and 40 are rejected under 35 U.S.C. § 103 as being unpatentable over Criss et al. (U.S. Patent Publn Num.: 2019/0042358 A1, cited in IDS), hereinafter Criss in view of Chen et al. (NPL “Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses”), hereinafter Chen.
Regarding claim 22, the rejection of claim 21 is incorporated as given above. Criss does not distinctly disclose wherein the one or more processor cores are configured to: send a first write portion of the plurality of write portions to the memory by a first pseudo channel of the memory; and send a second write portion of the plurality of write portions to the memory by a second pseudo channel of the memory.
Chen, in the same field of endeavor, teaches wherein the one or more processor cores are configured to: send a first write portion of the plurality of write portions to the memory by a first pseudo channel of the memory (Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).”); and send a second write portion of the plurality of write portions to the memory by a second pseudo channel of the memory (Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Criss with that of Chen so that write portions are sent to memory using first and second pseudo channels of the memory because such a system results in dependable and strong reliability, low energy consumption with strong error detection and correction capabilities. (Chen, see page 647, left column, third paragraph).
Regarding claim 23, the rejection of claim 21 is incorporated as given above. Criss does not distinctly disclose wherein the one or more processor cores are configured to: divide a write request identifying the data to be written to the memory into the plurality of write portions based on a number of channels of the memory.
Chen, in the same field of endeavor, teaches wherein the one or more processor cores are configured to:
divide a write request identifying the data to be written to the memory into the plurality of write portions based on a number of channels of the memory (Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).” See Fig. 2, 32B access versus 64B access).
The motivation to combine for claim 23 is the same as motivation to combine for claim 22.
Regarding claim 26, the rejection of claim 21 is incorporated as given above. Criss does not distinctly disclose further comprising the memory, wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
Chen, in the same field of endeavor, teaches further comprising the memory, wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory (Chen, page 646, section 1, left column “3D DRAMS, e.g., high bandwidth memory (HBM)”. Section “2.1 3D High Bandwidth Memory Architecture” shows in Fig. 2 3D stacked memory that is clocked/synchronous).
The motivation to combine for claim 26 is the same as motivation to combine for claim 22.
Regarding claim 31, the rejection of claim 30 is incorporated as given above. Criss does not distinctly disclose wherein the one or more processor cores are configured to: send a first fetch portion of the plurality of fetch portions to the memory by a first pseudo channel of the memory; and send a second fetch portion of the plurality of fetch portions to the memory by a second pseudo channel of the memory.
Chen, in the same field of endeavor, teaches wherein the one or more processor cores are configured to: send a first fetch portion of the plurality of fetch portions to the memory by a first pseudo channel of the memory (Under BRI, the Examiner interprets as identifying the bits in appropriate burst BL0 (B0-B31), BL1 …BL7 that is sent to memory and memory returns the data using pseudo channel of the memory. Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).” Thus, Chen teaches send a first fetch portion to return data using pseudo channel); and send a second fetch portion of the plurality of fetch portions to the memory by a second pseudo channel of the memory (Under BRI, the Examiner interprets as identifying the bits in appropriate burst BL0, BL1 …BL7 that is sent to memory and memory returns the data using pseudo channel of the memory. Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).” Thus, Chen teaches send a second fetch portion to return data using pseudo channel).
The motivation to combine for claim 31 is the same as motivation to combine for claim 22.
Regarding claim 33, the rejection of claim 28 is incorporated as given above. Criss does not distinctly disclose wherein the one or more processor cores are configured to: receive a first fetch return of the plurality of fetch returns from a first pseudo channel of the memory; and receive a second fetch return of the plurality of fetch returns from a second pseudo channel of the memory.
Chen, in the same field of endeavor, teaches wherein the one or more processor cores are configured to: receive a first fetch return of the plurality of fetch returns from a first pseudo channel of the memory (Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).”); and receive a second fetch return of the plurality of fetch returns from a second pseudo channel of the memory (Chen, Fig. 2, page 647, section 2.1, second paragraph “For each read or write operation, data is accessed from a single bank. …focus on the pseudo channel mode which has lower [activation] power and higher bandwidth. In this mode, a single channel is divided into two sub-channels each of size 64 bits and so a 32B access is transferred through 4 bursts (2 cycles). In a 64B access, two subchannels are activated at the same time and the 64B access is also transferred through 4 bursts (2 cycles).”).
The motivation to combine for claim 33 is the same as motivation to combine for claim 22.
Claims 35-36 and 40, the method that implements the apparatus of claims 22-23 and 26, respectively, are rejected on the same grounds as claims 22-23 and 26.
Conclusion
The prior art made of record in Form PTO-892 and below that are not relied upon are considered pertinent to Applicants’ disclosure. Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Callander (U.S. Patent No. 5,233,616) teaches a write-back cache which is protected with parity and error correction coding ("ECC"). The parity and ECC codes are generated by a memory interface when data is transferred by main memory to the central processing unit ("CPU") associated with the cache. Thus, all data originating in main memory will be parity and ECC encoded when it passes through the memory interface, and the data, and its related parity information and ECC codes will be stored in the cache. On the other hand, data which is taken from the cache and modified by the CPU during its processing operations is also transferred to the memory interface for ECC encoding. Thus, all data modified by the CPU is also protected, and the modified data, and its related parity information and ECC codes are also stored in the cache. The memory interface also contains ECC checking and correcting circuitry which can correct erroneous data, on the basis of its ECC code, if that data has been corrupted while stored in the cache, or during transmission on a bus. Therefore, if data in the cache is corrupted, it can be corrected when it is returned to main memory via the memory interface. Accordingly, the invention makes a write-back cache compatible with full ECC protection, even though, at times, the cache may contain the only correct, current copy of given data in the system.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
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/INDRANIL CHOWDHURY/ Examiner, Art Unit 2114
/ASHISH THOMAS/ Supervisory Patent Examiner, Art Unit 2114