Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is Non-Final
Claims 21-22, 24, 26-27, 34, 37, and 40 are rejected under nonstatutory double patenting
Claims 23, 25, 28-33, 35-36, and 38-39 are objected to as containing allowable subject matter
Information Disclosure Statement
The information disclosure statements (IDS) filed on February 2nd, 2026, February 18th, 2026, May 13th, 2026, and July 10th, 2026, have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-22, 24, and 26-27 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 and 17-19 of U.S. Patent No. 12,013,752 in view of Wikipedia, “Central Processing Unit,” 2021. Claims 10 and 17-19 of U.S. 12,013,752 teach the limitations of Claims 21-22, 24, and 26-27, except that the processing device comprises one or more processor cores; however, Wikipedia discloses this feature (Pages 1, 9, 10, and 17). Therefore, it would have been obvious to one of ordinary skill in the art to have the processing device comprise one or more cores, as multiple cores can lead to better performance (Page 17).
Claims 34, 37, and 40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-18 of U.S. Patent No. 12,013,752. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 17 and 18 in combination are narrower than claim 34.
Claim
Element
Reference Claim
Reference element
Differences
21
A processing device,
17
… at a processing device …
comprising: one or more processor cores configured to:
Wikipedia
*see above
generate a corresponding check value for each write portion of a plurality of write portions,
17
generating, … a check value for each write portion of a plurality of write portions …
a check value for each write portion corresponds to each write portion
each write portion of the plurality of write portions identifying a corresponding portion of data to be written to a memory coupled to the processing device
17
… each write portion of the plurality of write portions identifying a respective portion of data to be written to a memory;
The type of coupling is not defined, and thus the memory and processing device being able to communicate with each other is interpreted as a coupling
and identifying the corresponding check value associated with the write portion;
17
generating, … a check value for each write portion of a plurality of write portions …
Generating and identifying are both interpreted as finding or selecting a value since no further details are given, and thus are patentably indistinct
and send the plurality of write portions to the memory, wherein the memory is configured to write the data identified by the plurality of write portions, corresponding check values of the plurality of write portions, and write parity data to the memory,
17
… each write portion of the plurality of write portions identifying a respective portion of data to be written to a memory;
sending, to the memory, the write portions, check values, and write parity.
the write parity data based on the corresponding portions of the data identified by the plurality of write portions.
17
… a write parity based on the respective portions of data to be written to the memory of each write portion of the plurality of write portions and an operation;
22
The processing device of claim 21, wherein the one or more processor cores are configured to:
*see above
send a first write portion of the plurality of write portions to the memory by a first pseudo channel of the memory;
19
a first number of the write portions are sent to the memory on a first pseudo channel of the memory
Both claims refer to multiple write portions
and send a second write portion of the plurality of write portions to the memory by a second pseudo channel of the memory.
19
and a second number of the write portions are sent to the memory on a second pseudo channel of the memory.
24
The processing device of claim 21, wherein the one or more processor cores are configured to:
*see above
generate the write parity data based on one or more operations and the plurality of write portions.
17
determining a write parity based on the respective portions of data to be written to the memory of each write portion of the plurality of write portions and an operation;
Determining and generating are considered to be synonymous due to lack of further description
“an operation” is narrower than “one or more operations”
26
A system comprising the processing device of claim 21 and further comprising the memory, wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
18
wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
27
A processing device, comprising: one or more processor cores configured to:
10 + Wikipedia
a processing device … the processing device configured to:
*see above
based on a check bit indicating a fetch return of a plurality of fetch returns includes a fault, reconstruct the fetch return based on parity fetch data associated with the plurality of fetch returns and based on one or more other fetch returns of the plurality of fetch returns.
10
based on a check bit indicating a fetch return of a plurality of fetch returns includes a fault, reconstruct the fetch return based on a parity fetch associated with the plurality of fetch returns and based on one or more other fetch returns of the plurality of fetch returns;
34
A method, comprising:
17
A method comprising:
generating, by a processing device coupled to
17
generating, at a processing device,
The type of coupling is not defined, and thus the memory and processing device being able to communicate with each other is interpreted as a coupling
a stacked memory,
18
wherein the memory comprises … stacked … memory.
The reference more narrowly claims a specific type of stacked memory
a corresponding check value for each write portion of a plurality of write portions, each write portion of the plurality of write portions identifying a respective portion of data to be written to
17
… a check value for each write portion of a plurality of write portions … each write portion of the plurality of write portions identifying a respective portion of data to be written to a memory;
a check value for each write portion corresponds to each write portion
the stacked memory
18
wherein the memory comprises … stacked … memory.
and identifying the corresponding check value associated with the write portion;
17
generating … a check value for each write portion of a plurality of write portions …
Generating and identifying are both interpreted as finding or selecting a value since no further details are given, and thus are patentably indistinct
and writing, to the
17
to be written to a memory; and sending, to the memory, …
The reference claim describes writing
stacked memory,
18
wherein the memory comprises … stacked … memory.
See above
the plurality of write portions, corresponding check values, and write parity data,
wherein the write parity data is based on the respective portions of data to be written to the
17
each write portion of the plurality of write portions identifying a respective portion of data …
… the write portions, check values, and write parity.
a write parity based on the respective portions of data to be written to the memory
stacked memory
18
wherein the memory comprises … stacked … memory.
See above
identified by the plurality of write portions.
17
each write portion of the plurality of write portions identifying a respective portion of data to be written to a memory;
37
The method of claim 34, further comprising: generating the write parity data based on one or more operations and the plurality of write portions.
17
determining a write parity based on the respective portions of data to be written to the memory of each write portion of the plurality of write portions and an operation;
The reference claim is narrower because it has one operation instead of one or more operations
40
The method of claim 34, wherein the stacked memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
18
wherein the memory comprises a three-dimensional stacked synchronous dynamic random-access memory.
Allowable Subject Matter
Claims 23, 25, 28-33, 35-36, and 38-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 21-40 are not rejected under the prior art.
Although references cited teach parts of the method or the structure of the invention, the combination of all of the parts of the method being executed using the claimed structure was not found. Specifically, while multi-level error correction is known, as cited below and by Applicant, the specific method of which types of error correction are done by the processor and the memory cannot be found in the art or reasonably combined. Thus, the independent claims, Claims 21, 27, and 34, are not rejected under the prior art. The dependent claims, Claims 22-26, 28-33, and 35-40 are also not rejected under the prior art due to being a part of this combination. Claims 23, 25, 28-33, 35-36, and 38-39 are not rejected under double patenting, and thus are objected to as containing allowable matter. Applicant may choose to file a terminal disclaimer or amend the claims further to overcome all rejections.
Response to Arguments
Applicant's arguments filed on March 24th, 2026, have been fully considered but not all are persuasive.
The rejections under 35 U.S.C. 112 have been withdrawn due to the amendment.
Arguments regarding the newly amended claims as not being covered by the art are convincing. For further details on matter not rejected under the prior art, please see above.
Arguments regarding the rejections under non-statutory double patenting are not convincing. Amended features are still anticipated or obvious by the claims of the reference and are not patentably distinct. Please see above for further details.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Achtenberg et al. (U.S. Patent No. 10,002,086 B1): teaches parity use in a 3D stacked memory
Boehm et al. (U.S. Publication No. 2021/0248033 A1): teaches use of parity and ECC
Lu (U.S. Patent No. 12,126,358 B2): teaches multilevel error correction
Rambus Press, “High Bandwidth Memory (HBM): Everything You Need to Know,” 2026: teaches the benefits of pseudo-channels
Schaefer et al. (U.S. Publication No. 2020/0278908 A1): teaches error detection in a 3D memory
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/G.K.S./Examiner, Art Unit 2113
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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