DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hiyama (US 20080198526 A1 hereinafter Hiyama) in view of Peterson (US 20050184721 A1 hereinafter Peterson).
As to claim 1, Hiyama discloses in Figs. 1-12, a current sensing circuit (overcurrent protective circuit 14 sensing collector current through IGBT 11 as shown in Fig. 1, see the abstract, and also [0035]) configured to sense a current through a power switch (IGBT 11 as shown in Fig. 1, [0035]), the current sensing circuit comprising: a comparator (comparator 22 as shown in Fig. 1) having a first terminal and a second terminal (comparator 22 with input for V_sense and V_ref as shown in Fig. 1, [0037]); a first sensing branch (path from sense terminal (first node) of IGBT 11 to comparator input via sense resistor 12 as shown in Fig. 1) configured to couple a first node of the power switch with the first terminal of the comparator via a first reference resistor (path from sense terminal (first node) of IGBT 11 to comparator input via sense resistor 12 as shown in Fig. 1, [0036]); and an offset unit (correction current generating circuit 13 as shown in Fig. 1) configured to generate a reference current on the first sensing branch (correction current generating circuit 13 generating I_correct on the branch at first end of sense resistor 12 as shown in Fig. 1, [0040]),
Hiyama does not explicitly disclose the reference current being proportional to a replica voltage across a replica device of the power switch in the manner where the voltage drop (e.g., VDS) is directly used to generate the proportional current via mirroring.
However, Peterson teaches, in the same field of current sensing circuits for power switches (Figs. 1-3; [0001]-[0002]), generating a reference current proportional to a replica voltage across a replica device (sense FET 101 with op-amp matching VDS to main power FET, generating mirrored currents I1' and I2' proportional to voltage drop across sense FET via current mirrors 231-233, outputting M*(I2' - I1') proportional to sense current and thus to VDS per FET equations; Figs. 1-2, [0015]-[0023], [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyama's offset unit to generate the reference current proportional to the replica voltage across the replica device as taught by Peterson, in order to improve sensing accuracy by directly tracking the replica's voltage drop for better PVT compensation and reduced noise, as motivated by Peterson ([0011]-[0014], [0024]).
As to claim 2, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the offset unit comprises the replica device (current sensing element (replica) as shown in Fig. 12 (Hiyama), [0008]-[0009]; sense FET 101 as shown in Fig. 1 (Peterson), [0015]) and a current source which is configured to generate a replica current through the replica device (current source for sense current (replica current) at shunt ratio through it as shown in Fig. 12 (Hiyama), [0008]-[0009]; current mirrors generating replica currents I1'/I2' as shown in Fig. 2 (Peterson), [0020]-[0023]), thereby generating the replica voltage (generating V_sense as shown in Fig. 12 (Hiyama), [0008]-[0009]; VDS across sense FET as shown in Fig. 1 (Peterson), [0016]); and the replica current depends on a target value for the current through the power switch (sense current depends on SC trip level/target collector current as shown in Fig. 3 (Hiyama), [0041]; target based on mirror ratios K/M as shown in Fig. 2 (Peterson), [0023]).
As to claim 3, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), further comprising: a second sensing branch (path from emitter/ground (second node) to V_ref input via reference voltage generating circuit 21 components as shown in Fig. 1 (Hiyama)) configured to couple a second node of the power switch with the second terminal of the comparator via a second reference resistor (path from emitter/ground (second node) to V_ref input via reference voltage generating circuit 21 components as shown in Fig. 1 (Hiyama), [0037]).
As to claim 4, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the offset unit comprises an offset resistor (filter resistor 34 in correction path as shown in Figs. 9-11 (Hiyama), [0050]); and the offset unit is configured to generate the reference current based on the replica voltage using the offset resistor (I_correct generated based on temperature/replica behavior using filter resistor 34 as shown in Figs. 9-11 (Hiyama), [0053]; based on VDS voltage drop as shown in Fig. 1 (Peterson), [0016]-[0023]).
As to claim 5, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the
first reference resistor (sense resistor 12 as shown in Figs. 4-6 (Hiyama), [0045]), the second reference resistor (reference components in 21 as shown in Figs. 4-6 (Hiyama), [0045]) and the offset resistor (filter resistor 34 as shown in Figs. 4-6 (Hiyama), [0045]) each have a temperature dependency (each with temperature effects compensated as shown in Figs. 4-6 (Hiyama), [0045]; PVT tracking as taught in [0011] (Peterson)); and the temperature dependency of the first reference resistor, the second reference resistor and the offset resistor deviate by less than 10% from one another (compensation maintains constant operative level, implying matched dependencies within small deviation as shown in Fig. 5 (Hiyama), [0045]; via trimming for accuracy as taught in [0024] (Peterson)).
As to claim 6, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the offset unit comprises an offset transistor which is arranged in series with the offset resistor (transistors in correction circuit 13 arranged with filter resistor 34 as shown in Figs. 9-11 (Hiyama), [0050]; FETs 216-217 in series paths as shown in Fig. 2 (Peterson)); and an operational amplifier which is configured to set the reference current through the offset transistor in dependence of (op-amp in temperature-current conversion setting I_correct dependent on voltage drops as shown in Fig. 6 (Hiyama), [0046]; voltage-following op-amp setting currents I1/I2 as shown in Fig. 1 (Peterson), [0018]-[0020]) a voltage drop across the offset resistor which is caused by the reference current (op-amp in temperature-current conversion setting I_correct dependent on voltage drops as shown in Fig. 6 (Hiyama), [0046]; VDS drop as shown in Fig. 1 (Peterson), [0016]); and the replica voltage across the replica device (dependent on temperature affecting replica V_CE as shown in Fig. 6 (Hiyama), [0046]; VDS across sense FET as shown in Fig. 1 (Peterson), [0016]).
As to claim 7, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the operational amplifier is configured to set the reference current through the offset transistor such that the voltage drop across the offset resistor deviates from the replica voltage across the replica device by less than 10% (op-amp sets I_correct to maintain constant level, implying deviation less than 10% as shown in Fig. 5 simulation (Hiyama), [0045]; op-amp forces equal VDS for matching within small deviation as shown in Fig. 1 (Peterson), [0016]-[0018]).
As to claim 8, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the offset transistor is coupled to the first sensing branch via clamping transistor (transistors in correction circuit coupled to branch at node N1 via components as shown in Fig. 1 (Hiyama), [0040]), to provide the reference current to the first sensing branch (transistors in correction circuit coupled to branch at node N1 via components as shown in Fig. 1 (Hiyama), [0040]; via current mirrors as shown in Fig. 2 (Peterson), [0020]); and a gate of the replica device is coupled to an intermediate node between the offset transistor and the clamping transistor (gate electrode shared with main switching element as shown in Fig. 12 (Hiyama), [0009]; gate input to sense FET as shown in Fig. 2 (Peterson)).
As to claim 9, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the current sensing circuit is configured such that a first current through the first reference resistor corresponds to the sum of the reference current and a common-mode biasing current which is drawn by the first terminal of the comparator (current through sense resistor 12 = I_sense + I_correct, with comparator drawing negligible bias due to high impedance as shown in Fig. 1 (Hiyama), [0051]; sum of mirrored currents as shown in Fig. 2 (Peterson), [0023]).
As to claim 10, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the comparator is configured to draw symmetrical and/or identical common-mode biasing currents on the first sensing branch and on the second sensing branch (comparator 22 with high input impedance draws minimal/symmetrical currents on inputs as shown in Fig. 1 (Hiyama), [0051]).
As to claim 11, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the replica device is a replica of the power switch with regards to process, voltage and/or temperature behavior (current sensing element identical cell structure to switching element, tracking PVT as shown in Fig. 12 (Hiyama), [0008]-[0013]; sense FET matches main FET for PVT as taught in [0011] (Peterson)).
As to claim 12, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the reference current is injected to the first sensing branch at an intermediate node between the first reference resistor and the first terminal of the comparator (I_correct injected at node N1 between sense resistor 12 and comparator input as shown in Fig. 1 (Hiyama), [0036]).
As to claim 13, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the current sensing circuit comprises a second offset unit configured to generate a second reference current on the second sensing branch (reference voltage circuit 21 generating V_ref with internal offsets as shown in Fig. 1 (Hiyama), [0037]), such that the second reference current is proportional to a second replica voltage across a second replica device of the power switch (reference voltage circuit 21 generating V_ref with internal offsets proportional to parameters as shown in Fig. 1 (Hiyama), [0037]; proportional via mirroring as taught in [0023] (Peterson)).
As to claim 14, Hiyama discloses in Figs. 1-12, a power converter (semiconductor device with IGBT 11 for power conversion as shown in Fig. 1, [0035]) comprising: a power switch (IGBT 11 as shown in Fig. 1, [0035]); a current sensing circuit according to claim 1 (overcurrent protective circuit 14 as shown in Fig. 1, [0037]), configured to sense a current through the power switch (overcurrent protective circuit 14 sensing collector current through IGBT 11 as shown in Fig. 1, [0037]); and a control unit (driving circuit 15 as shown in Fig. 1, [0039]) configured to control the power switch in dependence of the sensed current through the power switch (driving circuit 15 stopping drive based on stop signal from sensed current as shown in Fig. 1, [0039]).
Hiyama does not explicitly disclose the current sensing circuit including the reference current being proportional to a replica voltage across a replica device of the power switch in the manner where the voltage drop (e.g., VDS) is directly used to generate the proportional current via mirroring.
However, Peterson teaches, in the same field of current sensing circuits for power switches (Figs. 1-3; [0001]-[0002]), a current sensing circuit with a reference current proportional to a replica voltage across a replica device (sense FET 101 with op-amp matching VDS to main power FET, generating mirrored currents I1' and I2' proportional to voltage drop across sense FET via current mirrors 231-233, outputting M*(I2' - I1') proportional to sense current and thus to VDS per FET equations; Figs. 1-2, [0015]-[0023], [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyama's current sensing circuit to include the reference current proportional to the replica voltage across the replica device as taught by Peterson, in order to improve sensing accuracy by directly tracking the replica's voltage drop for better PVT compensation and reduced noise in the power converter, as motivated by Peterson ([0011]-[0014], [0024]).
As to claim 15, Hiyama discloses in Figs. 1-12, a method for sensing a current through a power switch (method of overcurrent protection sensing collector current through IGBT 11 as shown in Fig. 1, see the abstract, and also [0038]), the method comprising: coupling a first node of the power switch with a first terminal of a comparator via a first sensing branch with a first reference resistor (coupling sense terminal (first node) of IGBT 11 to comparator input via sense resistor 12 as shown in Fig. 1, [0036]); coupling a second node of the power switch with a second terminal of the comparator via a second sensing branch with a second reference resistor (coupling emitter/ground (second node) to V_ref input via reference voltage generating circuit 21 components as shown in Fig. 1, [0037]); and generating a reference current on the first sensing branch (generating I_correct on the branch at first end of sense resistor 12 as shown in Figs. 1 and 4-6, [0040], [0045]),
Hiyama does not explicitly disclose the reference current being proportional to a replica voltage across a replica device of the power switch in the manner where the voltage drop (e.g., VDS) is directly used to generate the proportional current via mirroring.
However, Peterson teaches, in the same field of current sensing methods for power switches (Figs. 1-3; [0001]-[0002]), generating a reference current proportional to a replica voltage across a replica device (sense FET 101 with op-amp matching VDS to main power FET, generating mirrored currents I1' and I2' proportional to voltage drop across sense FET via current mirrors 231-233, outputting M*(I2' - I1') proportional to sense current and thus to VDS per FET equations; Figs. 1-2, [0015]-[0023], [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiyama's method to generate the reference current proportional to the replica voltage across the replica device as taught by Peterson, in order to improve sensing accuracy by directly tracking the replica's voltage drop for better PVT compensation and reduced noise, as motivated by Peterson ([0011]-[0014], [0024]).
As to claim 16, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein generating the reference current comprises generating a replica current through the replica device (sense current through current sensing element as shown in Fig. 12 (Hiyama), [0009]), thereby generating the replica voltage (generating V_sense as shown in Fig. 12 (Hiyama), [0009]; VDS as shown in Fig. 1 (Peterson), [0016]); and the replica current depends on a target value for the current through the power switch (depends on SC trip/target as shown in Fig. 3 (Hiyama), [0041]).
As to claim 17, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein generating the reference current comprises generating the reference current based on the replica voltage using an offset resistor (using filter resistor 34 as shown in Figs. 9-11 (Hiyama), [0053]; based on VDS as shown in Fig. 1 (Peterson), [0016]).
As to claim 18, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the first reference resistor (sense resistor 12 as shown in Figs. 4-6 (Hiyama), [0045]), the second reference resistor (reference components in 21 as shown in Figs. 4-6 (Hiyama), [0045]) and the offset resistor (filter resistor 34 as shown in Figs. 4-6 (Hiyama), [0045]) each have a temperature dependency (as shown in Figs. 4-6 (Hiyama), [0045]); and the temperature dependency of the first reference resistor, the second reference resistor and the offset resistor deviate by less than 10% from one another (matched via compensation as shown in Fig. 5 (Hiyama), [0045]).
As to claim 19, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein generating the reference current comprises setting the reference current through an offset transistor which is arranged in series with the offset resistor in dependence of (setting via op-amp and transistors with filter resistor 34 as shown in Figs. 6 and 9-11 (Hiyama), [0046], [0050]) a voltage drop across the offset resistor which is caused by the reference current (setting via op-amp and transistors with filter resistor 34 as shown in Figs. 6 and 9-11 (Hiyama), [0046], [0050]; VDS drop as shown in Fig. 1 (Peterson), [0016]); and the replica voltage across the replica device (dependent on replica V_CE as shown in Fig. 6 (Hiyama), [0046]; VDS as shown in Fig. 1 (Peterson), [0016]).
As to claim 20, Hiyama in view of Peterson discloses in Figs. 1-12 (Hiyama) and Figs. 1-3 (Peterson), wherein the reference current through the offset transistor is set such that the voltage drop across the offset resistor deviates from the replica voltage across the replica device by less than 10% (set to maintain constant, implying <10% deviation as shown in Fig. 5 (Hiyama), [0045]; op-amp forces matching within small deviation as shown in Fig. 1 (Peterson), [0016]-[0018]).
Conclusion
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 1/5/25