Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: the disclosure sets forth multiple instances of “control circuity”. For purposes of compact prosecution, this is being interpreted as “control circuitry”.
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 6, 12, 13, and 18 set forth “control circuity”. Each instance of “control circuity” is being interpreted as “control circuitry”. Appropriate clarification is required.
Claims 2-6 are objected to as dependent upon claim 1 and claims 14-20 are objected to as dependent upon claim 13.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the memory array" in line 5. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Claims 2-6 are rejected as dependent upon claim 1.
Claim 1 sets forth “and wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.” This language requires that “the unselected word lines” are biased to the read pass voltage throughout the entire “first read operation and the second read operation”.
Claim 1 sets forth “perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage” as well as “perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage”.
This language is indefinite and it is not clear to one of ordinary skill in the art how to make and/or use such an invention. For example, if the unselected word lines are biased to the read pass voltage “during and between” the first read operation and the second read operation, it is unclear how a plurality of such unselected word lines are to be biased to the read pass voltage if they are already biased to the read pass voltage and at no time are to be “discharged”. Further, the claim includes syntactic ambiguity which renders the intended meaning of the claim limitation “biased” unclear in each instance of the word. Appropriate clarification is required.
Claims 2-6 are rejected as dependent upon claim 1.
Claim 7 sets forth “and wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.” This language requires that “the unselected word lines” are biased to the read pass voltage throughout the entire “first read operation and the second read operation”.
Claim 7 sets forth “perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage” as well as “perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage”.
This language is indefinite and it is not clear to one of ordinary skill in the art how to make and/or use such an invention. For example, if the unselected word lines are biased to the read pass voltage “during and between” the first read operation and the second read operation, it is unclear how a plurality of such unselected word lines are to be biased to the read pass voltage if they are already biased to the read pass voltage and at no time are to be “discharged”. Further, the claim includes syntactic ambiguity which renders the intended meaning of the claim limitation “biased” unclear in each instance of the word. Appropriate clarification is required.
Claims 8-12 are rejected as dependent upon claim 7.
Claim 13 recites the limitation "the memory array" in line 7. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Claims 14-20 are rejected as dependent upon claim 13.
Claim 13 sets forth “and wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.” This language requires that “the unselected word lines” are biased to the read pass voltage throughout the entire “first read operation and the second read operation”.
Claim 13 sets forth “perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage” as well as “perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage”.
This language is indefinite and it is not clear to one of ordinary skill in the art how to make and/or use such an invention. For example, if the unselected word lines are biased to the read pass voltage “during and between” the first read operation and the second read operation, it is unclear how a plurality of such unselected word lines are to be biased to the read pass voltage if they are already biased to the read pass voltage and at no time are to be “discharged”. Further, the claim includes syntactic ambiguity which renders the intended meaning of the claim limitation “biased” unclear in each instance of the word. Appropriate clarification is required.
Claims 14-20 are rejected as dependent upon claim 13.
Claim 13 sets forth “high bandwidth flash packages”. This term is unclear. The language “high bandwidth” is relative, and the disclosure does not appear to provide sufficient support as to indicate what is being considered “high” bandwidth in the claims. Appropriate clarification is required.
Claims 14-20 are rejected as dependent upon claim 13.
Due to indefiniteness in the claims, the intended meaning of the claims is unclear. (MPEP 2173.06: “where there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of a claim, it would not be proper to reject such a claim on the basis of prior art.”) In an attempt to promote compact prosecution, the below art-based mapping is based on a possible interpretation of the claims.
Relevant prior art is made of record:
US20230178160 (Liu, et al., hereinafter Liu).
Regarding claim 1, Liu teaches a memory device (Liu, “memory device”, FIG. 1-6), comprising: a memory block including a plurality of strings, (Liu, [0067]: “As shown in FIG. 6, in some implementations, memory cell array 602 in one block 603 may be provided in the form of an array of memory strings 606, such as NAND memory strings.”) each string comprising a plurality of non-volatile memory cells, (Liu, [0067]: “In some implementations, each of memory strings 606 may extend vertically above a substrate (not shown), and each may include a plurality of memory cells 604 coupled in series and stacked vertically.”) each non-volatile memory cell being coupled to one of a plurality of word lines; (Liu, [0072]: “Memory cells 604 of adjacent memory strings 606 in one block 603 can be coupled through word lines WLs that select which rows of memory cells 604 to be impacted,”) control circuity coupled to the memory array, (Liu, “control logic”) the control circuity being configured to; perform a first read operation (“read operation”) on a first non-volatile memory cell in the memory block (Liu, [0004]: “The first pass voltage may include a voltage applied to the first unselected word lines in the first read operation.”) while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage, (Liu, [0005]: “In some implementations, in the first read operation, the peripheral circuits may be configured to apply the first pass voltage to the first unselected word lines and the second unselected word lines.”) and perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage; (Liu, [0004]: “start a second read operation on the memory cell. In the second read operation, the peripheral circuits may be configured to apply a second pass voltage to first unselected word lines and a first pass voltage to second unselected word lines”) and wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation. (Liu, [0092]: “and in the first read operation, the pass voltage applied to all the unselected word lines may remain the same.”)
Regarding claim 7, Liu teaches a method of operating a memory device, (Liu, “memory device”, FIG. 1-6) comprising the steps of: preparing a memory block that includes a plurality of strings, (Liu, [0067]: “As shown in FIG. 6, in some implementations, memory cell array 602 in one block 603 may be provided in the form of an array of memory strings 606, such as NAND memory strings.”) each string comprising a plurality of non-volatile memory cells, (Liu, [0067]: “In some implementations, each of memory strings 606 may extend vertically above a substrate (not shown), and each may include a plurality of memory cells 604 coupled in series and stacked vertically.”) each non-volatile memory cell being coupled to one of a plurality of word lines; (Liu, [0072]: “Memory cells 604 of adjacent memory strings 606 in one block 603 can be coupled through word lines WLs that select which rows of memory cells 604 to be impacted,”) performing a first read operation (“read operation”) on a first non-volatile memory cell in the memory block (Liu, [0004]: “The first pass voltage may include a voltage applied to the first unselected word lines in the first read operation.”) while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage; (Liu, [0005]: “In some implementations, in the first read operation, the peripheral circuits may be configured to apply the first pass voltage to the first unselected word lines and the second unselected word lines.”) performing a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage; (Liu, [0004]: “start a second read operation on the memory cell. In the second read operation, the peripheral circuits may be configured to apply a second pass voltage to first unselected word lines and a first pass voltage to second unselected word lines”) and wherein the unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation. (Liu, [0092]: “and in the first read operation, the pass voltage applied to all the unselected word lines may remain the same.”)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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