DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/30/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, claim 1 recites, inter alia, “wherein a transconductance of the fourth transistor is greater than a transconductance of the third transistor”. The originally filed specification does not use the term “transconductance” and does not reasonably convey to one of ordinary skill in the art the concept of transconductance or a relationship between the transconductances of the transistors. While the specification describes relative strength of certain transistors and discusses weakening or strengthening pull-down behavior, however, the specification does not expressly or inherently describe transconductance (gm) or a comparison thereof. The specification must describe the claimed feature itself and not rely on what a person having ordinary skill in the art could infer abstractly and the jump from saying pull-down strength or weakened pull-down to transconductance is a step too far based on just how a person of ordinary skill in the art would interpret as transconductance deals with more aspects such as sizing (W/L), ratios between devices, bias currents, and other technological parameters allowing it to act like a gain knob for a transistor. The application does not highlight the sizing, ratios or bias currents and only highlights the functional behavior of having a higher current drive and being stronger. Know that something relates to transconductance is not the same as describing transconductance. Based on this reasoning the Examiner believes that the term “transconductance” recited in claim 1 is an introduction of new matter not properly supported by the originally filed specification. For purposes of examination, the Examiner has interpreted the limitation of “wherein a transconductance of the fourth transistor is greater than a transconductance of the third transistor” as “wherein a first pull-down strength of the fourth transistor is greater than a second pull-down strength of the third transistor”. The reason for this interpretation is based on what the specification of the immediate application points out in Paragraphs 0020 and 0023. Paragraph 0020 points out the pull-down strength is weakened and Paragraph 0023 recites “FET 202 is a weak device compared to FET 204. In one example, FET 204 is eight to ten times stronger than FET 202”. Claims 2-10 are also rejected due to being dependent upon claim 1 therefore inheriting the deficiencies of claim 1.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 11-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0336140 A1) in view of Kaya (US 2008/0061867 A1).
Regarding claim 1 (See 112(a) Rejection above for Interpretation), Liu teaches an integrated circuit (Figure 6; Figure 1 shows the overall block diagram of the circuit) comprising: a first transistor (Figure 6 Component 611) coupled to a switching terminal (Figure 6 Component 605), the first transistor including a control terminal (Figure 6 Component 611 gate terminal), a first current terminal (Figure 6 Component 611 drain terminal), and a second current terminal (Figure 6 Component 611 source terminal); a second transistor (Figure 6 Component 622) coupled to the switching terminal (Figure 6 Component 622 has a drain terminal coupled to Component 605), the first transistor and the second transistor coupled in series (Figure 6 Components 611 and 622 are coupled in series); a third transistor (Figure 6 Component 610 is a gate driver circuit wherein the gate driver circuit is described in detail with reference to Figure 3 therefore Figure 3 will be referenced to show these Components for more accurate mapping; Figure 3 Component 320; Figure 6 Component 610 bottom right transistor correlates with Component 320 in Figure 3) coupled between the control terminal of the first transistor and the switching terminal (Figure 6 Component 610 bottom right transistor which correlates with Component 320 in Figure 3 is coupled between the gate terminal of Component 611 and Component 605); a fourth transistor (Figure 3 Component 330; Figure 6 Component 610 bottom left transistor correlates with Component 330 in Figure 3) coupled between the control terminal of the first transistor and the switching terminal (Figure 6 Component 610 bottom left transistor which correlates with Component 330 in Figure 3 is coupled between the gate terminal of Component 611 and Component 605), wherein a transconductance of the fourth transistor is greater than a transconductance of the third transistor (Paragraph 0040 “a second NMOS transistor 330 that is connected in parallel with the first NMOS transistor 320… the first NMOS transistor may be a small transistor that is capable of conducting less current than the second NMOS transistor”; This passage highlights that Component 330 can be designed as a larger transistor thus meaning more current which leads it having a stronger pull-down strength than Component 320); and a circuit coupled to the control terminal of the first transistor (Figure 1 Component 110 sends control signals to driver circuits which then send signals to Component 611 in Figure 6 thus Component 110 is coupled to the gate of Component 611 through those control components).
Liu does not teach the circuit configured to turn off the third transistor responsive to a drop in a voltage at the second current terminal of the first transistor.
Kaya teaches an integrated circuit (Figure 12), comprising: a first transistor (Figure 12 Component 1115) having a second current terminal coupled to a switching terminal (Figure 12 Component 1115 bottom terminal is coupled to Component 1110); a gate pull down circuit (Figure 12 Component 1254) including a third transistor (Figure 12 Component 1266) and a fourth transistor (Figure 12 Component 1262); and a circuit coupled to the gate terminal of the first transistor (Figure 12 Components 1282+1294+1298+1286+1274+1135), configured to turn off the third transistor responsive to a drop in a voltage at the second current terminal of the first transistor (Paragraph 0078 “the first and second pull-down FETs 1262 and 1266 provide a high pull-down strength (e.g., corresponding to a low resistance path to the voltage output 1110) for the high-side pull-down circuit 1254 when both FETs are initially turned ON. As discussed above in connection with FIG. 11, this high pull-down strength causes the high-side FET 1115 to begin switching rapidly to the OFF state. Then, at a later time when the output voltage 1110 decreases by a predetermined amount, the second pull-down FET 1266 is turned OFF to reduce the pull-down strength (e.g., corresponding to a higher resistance path to PGND 1130) for the high-side pull-down circuit 1254”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Liu to incorporate the control circuit controlling the third transistor to turn off in response to a voltage drop at a switching output terminal as taught by Kaya. The advantage of this modification is that it provides adaptive control of pull-down strength based on the switching node voltage thereby reducing reliance on predetermined timing sequences or load based control signals and improving the robustness of the system across varying operating conditions.
Regarding claim 2, Liu and Kaya teach all the limitations of claim 1. Liu further teaches wherein: the second current terminal of the first transistor is a source of a field effect transistor (Figure 6 Component 611 Source Terminal).
Regarding claim 3, Liu and Kaya teach all the limitations of claim 2. Liu further teaches wherein: the second current terminal of the first transistor is coupled to a drain of the second transistor (Figure 6 Component 611 Source Terminal is coupled to the Drain Terminal of Component 622).
Regarding claim 4, Liu and Kaya teach all the limitations of claim 1. Liu further teaches wherein: the fourth transistor is configured to turn on responsive to a signal from the circuit that is configured to turn off the first transistor (Figure 8 shows the control sequence; Step 860 shows that when the MOSFET, Component 611, is sent the signal to turn off then the 1st and 2nd transistors are turned ON).
Regarding claim 5, Liu and Kaya teach all the limitations of claim 1. Liu does not teach wherein: turning off the first transistor includes reducing a gate-to-source voltage of the third transistor.
Kaya teaches an integrated circuit (Figure 12), comprising: a first transistor (Figure 12 Component 1115) having a second current terminal coupled to a switching terminal (Figure 12 Component 1115 bottom terminal is coupled to Component 1110); a gate pull down circuit (Figure 12 Component 1254) including a third transistor (Figure 12 Component 1266) and a fourth transistor (Figure 12 Component 1262); and a circuit coupled to the gate terminal of the first transistor (Figure 12 Components 1282+1294+1298+1286+1274+1135), configured to turn off the third transistor responsive to a drop in a voltage at the second current terminal of the first transistor (Paragraph 0078 “the first and second pull-down FETs 1262 and 1266 provide a high pull-down strength (e.g., corresponding to a low resistance path to the voltage output 1110) for the high-side pull-down circuit 1254 when both FETs are initially turned ON. As discussed above in connection with FIG. 11, this high pull-down strength causes the high-side FET 1115 to begin switching rapidly to the OFF state. Then, at a later time when the output voltage 1110 decreases by a predetermined amount, the second pull-down FET 1266 is turned OFF to reduce the pull-down strength (e.g., corresponding to a higher resistance path to PGND 1130) for the high-side pull-down circuit 1254”), wherein turning off the first transistor includes reducing a gate-to-source voltage of the third transistor (Paragraph 0078 highlights the operation of pulling down the voltage at the first transistor to turn it off and highlights a control wherein the third transistor is turned off while the first transistor is turned off thus indicating the reduction of the gate-to-source voltage of the third transistor as Component 1266 is a NFET).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Liu to incorporate the control circuit controlling the third transistor to turn off in response to a voltage drop at a switching output terminal as taught by Kaya. The advantage of this modification is that it provides adaptive control of pull-down strength based on the switching node voltage thereby reducing reliance on predetermined timing sequences or load based control signals and improving the robustness of the system across varying operating conditions.
Regarding claim 6, Liu and Kaya teach all the limitations of claim 1. Liu further teaches wherein: responsive to the drop in the voltage at the second current terminal of the first transistor, the first transistor commutates current to the second transistor (This is the basic operation of a buck converter which is seen in Figure 6 wherein when the high side switch turns off the current goes through the low side switch; Paragraph 0046 “The HS-FET 611 and the LS-FET 612 are switched (i.e., at a switching frequency) by the gate drivers to alternatively connect an output inductor 630 to an input voltage (PVin) 650 and ground”; Paragraph 0051 highlights that the switching is based on sensing the load current which would be indicative of the voltage at the switching terminal).
Regarding claim 11, Liu teaches a system (Figure 6; Figure 1 shows the overall block diagram of the circuit) comprising: a first transistor (Figure 6 Component 611) including a control terminal (Figure 6 Component 611 gate terminal), a first current terminal (Figure 6 Component 611 drain terminal), and a second current terminal (Figure 6 Component 611 source terminal); a second transistor (Figure 6 Component 610 is a gate driver circuit wherein the gate driver circuit is described in detail with reference to Figure 3 therefore Figure 3 will be referenced to show these Components for more accurate mapping; Figure 3 Component 320; Figure 6 Component 610 bottom right transistor correlates with Component 320 in Figure 3) including a control terminal (Figure 3 Component 320 Gate Terminal), a first current terminal (Figure 3 Component 320 Drain Terminal), and a second current terminal (Figure 3 Component 320 Source Terminal), wherein the control terminal of the first transistor is coupled to the first current terminal of the second transistor (Figure 3 Component 320 drain terminal is shown to be connected to a gate of the power MOSFET shown in Figure 6); a third transistor (Figure 3 Component 330; Figure 6 Component 610 bottom left transistor correlates with Component 330 in Figure 3) including a control terminal (Figure 3 Component 330 Gate Terminal), a first current terminal (Figure 3 Component 330 Drain Terminal), and a second current terminal (Figure 3 Component 330 Source Terminal), wherein the control terminal of the first transistor is coupled to the first current terminal of the third transistor (Figure 3 Component 330 drain terminal is shown to be connected to a gate of the power MOSFET shown in Figure 6); and a controller circuit configured to turn off the first transistor by turning on the second transistor and the third transistor (Figure 1 Component 110 is the controller circuit which generates the signals to Components 320 and 330 as seen in Figures 3 and 6; Paragraph 0041 “Thus, when the first NMOS 320 and the second NMOS 330 operate together more charge can be drained from the gate of the power MOSFET over a period (i.e., higher current) than when either the first NMOS 320 or the second NMOS 330 operate alone. Accordingly, by controlling the on/off state of the second NMOS 330 while the first NMOS 320 is in an on state, the driving strength of the gate driver may be adjusted between one of two levels”; Paragraph 0039 highlights that the pull-down transistor are turned on to turn off Component 611).
Liu does not teach wherein in response to detecting that a voltage at the second current terminal of the first transistor reaches a set voltage during turn-off of the first transistor, the second transistor turns off.
Kaya teaches an integrated circuit (Figure 12), comprising: a first transistor (Figure 12 Component 1115) having a second current terminal coupled to a switching terminal (Figure 12 Component 1115 bottom terminal is coupled to Component 1110); a gate pull down circuit (Figure 12 Component 1254) including a second transistor (Figure 12 Component 1266) and a third transistor (Figure 12 Component 1262); and a control circuit coupled to the gate terminal of the first transistor (Figure 12 Components 1282+1294+1298+1286+1274+1135), configured to turn off the second transistor in response to detecting that a voltage at the second current terminal of the first transistor reaches a set voltage during turn-off of the first transistor (Paragraph 0078 “the first and second pull-down FETs 1262 and 1266 provide a high pull-down strength (e.g., corresponding to a low resistance path to the voltage output 1110) for the high-side pull-down circuit 1254 when both FETs are initially turned ON. As discussed above in connection with FIG. 11, this high pull-down strength causes the high-side FET 1115 to begin switching rapidly to the OFF state. Then, at a later time when the output voltage 1110 decreases by a predetermined amount, the second pull-down FET 1266 is turned OFF to reduce the pull-down strength (e.g., corresponding to a higher resistance path to PGND 1130) for the high-side pull-down circuit 1254”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Liu to incorporate the control circuit of Kaya and controlling the second transistor to turn off in response to a voltage drop at a switching output terminal as taught by Kaya. The advantage of this modification is that it provides adaptive control of pull-down strength based on the switching node voltage thereby reducing reliance on predetermined timing sequences or load based control signals and improving the robustness of the system across varying operating conditions.
Regarding claim 12, Liu and Kaya teach all the limitations of claim 11. Liu further teaches wherein: the first transistor is a high-side transistor for a switching voltage regulator (Figure 6 Component 611 is a high side transistor); the second transistor is a first pull-down transistor (Figure 3 Component 320 is a pull-down transistor); and the third transistor is a second pull-down transistor (Figure 3 Component 330 is a pull-down transistor).
Regarding claim 13, Liu and Kaya teach all the limitations of claim 11. Liu further teaches wherein: the controller circuit is configured to output a signal to turn off the first transistor (Paragraphs 0039-0041 highlight that the controller is configured to turn off the first transistor through the control signals).
Regarding claim 14, Liu and Kaya teach all the limitations of claim 13. Liu further teaches wherein: the control terminal of the third transistor is configured to receive the signal (Paragraph 0039 highlights that the controller sends the signal to Component 320 to turn on thus leading to a turn off of Component 611).
Regarding claim 19, Liu and Kaya teach all the limitations of claim 11. Liu further teaches wherein: the first current terminal of the first transistor is coupled to an inductor (Figure 6 Component 611 drain terminal is coupled to Component 602a which is a parasitic inductance; This element meets the claim limitation because Applicant in their own disclosure points out that their inductors are also parasitic inductances in Paragraph 0017).
Regarding claim 20, Liu and Kaya teach all the limitations of claim 11. Liu further teaches wherein: the second current terminal of the first transistor is coupled to the second current terminal of the second transistor and the second current terminal of the third transistor (Figure 6 Component 611 source terminal is coupled to the source terminals of the pull-down transistors shown).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2020/0336140 A1) in view of Kaya (US 2008/0061867 A1) and in further view of Kohout (US 2006/0244498 A1)
Regarding claim 15, Liu and Kaya teach all the limitations of claim 13. Liu does not teach a NAND gate including a first input, a second input, and an output.
Kaya teaches an integrated circuit (Figure 12), comprising: a first transistor (Figure 12 Component 1115) having a second current terminal coupled to a switching terminal (Figure 12 Component 1115 bottom terminal is coupled to Component 1110); a gate pull down circuit (Figure 12 Component 1254) including a second transistor (Figure 12 Component 1266) and a third transistor (Figure 12 Component 1262); and a control circuit coupled to the gate terminal of the first transistor (Figure 12 Components 1282+1294+1298+1286+1274+1135), configured to turn off the second transistor in response to detecting that a voltage at the second current terminal of the first transistor reaches a set voltage during turn-off of the first transistor (Paragraph 0078 “the first and second pull-down FETs 1262 and 1266 provide a high pull-down strength (e.g., corresponding to a low resistance path to the voltage output 1110) for the high-side pull-down circuit 1254 when both FETs are initially turned ON. As discussed above in connection with FIG. 11, this high pull-down strength causes the high-side FET 1115 to begin switching rapidly to the OFF state. Then, at a later time when the output voltage 1110 decreases by a predetermined amount, the second pull-down FET 1266 is turned OFF to reduce the pull-down strength (e.g., corresponding to a higher resistance path to PGND 1130) for the high-side pull-down circuit 1254”); and wherein: the control circuit is configured to output a signal to turn off the first transistor (Paragraph 0078) wherein the control circuit further includes an AND gate including a first input, a second input, and an output (Figure 12 Component 1298) in combination with inverters (Figure 12 Components 1294+1135).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Liu to incorporate the control circuit of Kaya and controlling the second transistor to turn off in response to a voltage drop at a switching output terminal as taught by Kaya. The advantage of this modification is that it provides adaptive control of pull-down strength based on the switching node voltage thereby reducing reliance on predetermined timing sequences or load based control signals and improving the robustness of the system across varying operating conditions.
Kahout teaches a gate driver circuit (Figure 5 Component 208) for driving a power MOSFET (Figure 5 Component 202) wherein the control circuit comprises a NAND gate having a first input, a second input and an output (Figure 5 Component 216 or 220).
It would have been obvious to one of ordinary skill in the art to modify the combined teaching of Liu and Kaya to incorporate using NAND gates instead of AND gates as taught by Kahout. The advantage of NAND gates is they are universal gates, allowing any boolean function to be built with fewer components which results in smaller CMOS circuit while also providing a faster CMOS circuit as well due to lower propagation delay.
Allowable Subject Matter
Claims 7-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the first current terminal of the fifth transistor is coupled to a control terminal of the third transistor, and the second current terminal of the fifth transistor is coupled to a second current terminal of the third transistor. Claims 8-10 depend upon claim 7.
Allowable Subject Matter
Claims are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 16, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein: the first input of the NAND gate is configured to receive the signal; and the second input of the NAND gate is configured to receive an enable signal. Claims 17-18 depend upon claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li (US 2020/0412361 A1) teaches a gate driver; a comparator input is adapted to be coupled through a resistor and a diode to a first transistor. A latch input is coupled to a comparator output. A second transistor has a first control terminal and a first output terminal. The first output terminal is adapted to be coupled to a control terminal of the first transistor. A third transistor is smaller than the second transistor. The third transistor has a second control terminal and a second output terminal. The second output terminal is adapted to be coupled to the control terminal of the first transistor. Control logic has a logic input and first and second logic outputs. The logic input is coupled to a latch output. The first logic output is coupled to the first control terminal. The second logic output is coupled to the second control terminal.
Hirler (US 2014/0015586 A1) teaches a bridge circuit that includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
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