DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "”the control logic circuits”" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination it will be assumed that the above recitation refers to the “control circuits”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 10-12 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu (USPAPN 2012/0286750).
With respect to claim 1, Xu discloses, in Figs. 1, 2, 5 and 6, a circuit (Fig. 6, wherein Fig. 6 discloses a multi-phase/interleaved embodiment of Fig. 1, see para 0033, Fig. 2 discloses the frequency modulation of circuitry, see paras 0017-0018, and Fig. 5 discloses the details of 118, see para 0030) comprising:
a timer circuit (118 of Fig. 6, details disclosed in Fig. 5) configurable to provide a timer signal (CLK) responsive to on an output voltage of a power converter (responsive to COMP which is responsive to Vout of the power converter comprising the switches connected to each 104a-104C with each 106a-106c. COMP is controlled by Vout under the control of 114); and
control circuits (each 104a-104b) coupled to the timer circuit (coupled to CLK via each 109a-109c), wherein each of the control circuits is configurable to provide pulses (pulses to the gates of the transistors of each power converter) and set a frequency of the pulses responsive to the timer signal (the pulses are set at frequency of the timer circuit, para 0017-0018).
With respect to claim 2, the circuit of claim 1, further comprising a rotator circuit (109a-109c) configurable to provide rotator signals (outputs of each phase splitter) to the control circuits (via each PWM), wherein control circuits are configurable to, responsive to the rotator signals and the timer signal (via PWM controlling each 104a-104c, wherein the output of each PWM is responsive to the CLK signal and the output of each 109a-109c), provide the pulses at different time periods (outputs of each 109a-109c at different phases, see para 0033 “[t]he individual phase splitters 109a, 109b, and 109c selectively enable the respective PWM controllers 104a, 104b, and 104c at different phase”).
With respect to claim 3, the circuit of claim 2, wherein the timer signal (CLK, see Fig. 5) has a triggered state (when CLK is pulsed) and a reset state (when 132 of Fig. 5 is activated long enough such that the inverting terminal of 138 is lower than Vosc_ref), and each of the control logic circuit is configurable to generate the respective pulses responsive to the timer signal transitioning to the triggered state and the respective rotator signal is active (the circuit is operated as claimed according to the pulsing of CLK, see Fig. 2).
With respect to claim 4, the circuit of claim 3, wherein the timer circuit is configurable to generate the timer signal responsive to on a comparison (comparison provided by 138 of Fig. 5) of a voltage ramp signal (signal on 138a/ramped signal on capacitor 134) and a timer reference voltage (signal on 138b/Vosc_ref).
With respect to claim 5, the circuit of claim 4, wherein the timer circuit is configurable to transition the timer signal to the triggered state responsive to the voltage ramp signal being greater than the timer reference voltage (pulsed high when 138a is larger than 138b), and transition the timer signal is transitioned to the reset state responsive to the voltage ramp signal being below the timer reference voltage (once 132 pulls 138a lower than 138b the timer signal is reset, i.e., 138 outputs a low and the clock is reset low).
With respect to claim 6, the circuit of claim 4, wherein the timer circuit is configurable to generate the voltage ramp signal is generated based responsive to a voltage control signal (COMP which controls the voltage on 134 via the mirror of 144 and 136 to 134 of Fig. 5) indicative of the output voltage (as controlled by 114 of Fig. 6) and a reset signal (signal on 138c controlling CLK via 140).
With respect to claim 10, the circuit of claim 6, further comprising a voltage compensation circuit (114 of Fig. 6) configurable to generate the voltage control signal (COMP) responsive to a comparison of a feedback voltage (voltage on the non-inverting terminal of 114) indicative of the output voltage (voltage at the non-inverting terminal is indicative of Vout via the resistor connected to the inverting terminal) and an output reference voltage (Vref to the non-inverting terminal).
With respect to claim 11, the circuit of claim 2, wherein the rotator circuit is configured to generate the plurality of rotator signals (output of each 109a-109c) responsive to on the timer signal (output of 109a-109c responsive to CLK, see paragraph 0033).
With respect to claim 12, a circuit (Fig. 6, further details disclosed in Figs. 1-2 and 5) comprising:
a first control circuit (PWM connected to 109a with 104a) having an input (input connected to 109a, e.g., non-inverting terminal of the PWM), and an output (at least one of the outputs of 104a connected to the transistors 102a);
a second control circuit (PWM connected to 109b with 104b) having an input (input connected to 109b, e.g., non-inverting terminal of the respective PWM) and an output (at least one of the outputs of 104b connected to the transistors 102b);
a first power stage (102a with 106a) and having an input coupled to the output of the first control circuit (at least one of the gates of 102a);
a second power stage (102b with 106b) having an input coupled to the output of the second control circuit (at least one of the gates of 102b); and
a timer circuit (118 further details disclosed in Fig. 5) having an input (input connected to COMP) and an output (CLK), the output coupled to the input of the first control circuit and to the input of the second control circuit (coupled via 109a and 109b), and the input of the timer circuit coupled to outputs (outputs via 106a and 106b at Vout) of the first and second power stages (via 114 to COMP).
With respect to claim 18, a system (system of Fig. 6 further details disclosed in Figs. 1, 2 and 5) comprising:
power converter circuits (102a with 16a and 102b with 106b), wherein an output terminal of each of the power converter circuits is coupled to a common output terminal (output terminal of each 106 connected to the Vout output terminal);
a timer circuit (118, further details disclosed in Fig. 5) configurable to provide a timer signal (CLK) responsive to an amplitude of an output voltage at the common output terminal of the power converter circuits (CLK is responsive to COMP which is responsive to the amplitude of Vout on the Vout output terminal); and
control circuits coupled to the timer circuit (104a and 104b coupled to CLK via 109a and 109b) and configurable to provide pulses (at least one of the outputs to the gates of 102a and 102b, respectively) and set a frequency of the pulses responsive to the timer signal (the gate control signals are set at a frequency responsive to CLK, see Fig. 2, via the control of CLK to 109a, 109b which controls 104a and 104b).
With respect to claim 19, the system of claim 18, further comprising a rotator circuit (109a with respective PWM and 109b with respective PWM) configurable to provide rotator signals to each of the control circuits (output of each respective PWM connected to 109a and 109b), wherein the control logic circuits are configurable to generate the pulses responsive to the timer signal and the rotator signals (the output of each of 104a and 104b are responsive to the CLK signal, since the CLK signal controls the frequency of the pulses, and the rotator signals, since the rotator signals control which phase/104a is activate temporally, see paragraph 0033).
With respect to claim 20, the system of claim 19, wherein the timer signal has a triggered state (when the voltage on 138a of Fig. 5 is higher than the voltage on 138b) and a reset state (when the voltage on 138a reaches a value lower than 138b when being pulled down by the activation of 132), and each of the control logic circuits is configurable to start generating the respective pulses responsive to the timer signal transitioning to the triggered state and the respective rotator signal is active (the circuit operates as claimed due to the pulsing of CLK in the triggered state and the rotator signals being generated responsive to the pulsing of the CLK signal).
Allowable Subject Matter
Claims 7-9 and 13-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849